公开(公告)号：US07262716B2

公开(公告)日：2007-08-28

申请号：US10325202

申请日：2002-12-20

申请人： Xianggang Yu ,  Terry L. Sculley ,  Jung-Kuei Chang

发明人： Xianggang Yu ,  Terry L. Sculley ,  Jung-Kuei Chang

IPC分类号： H03M7/00

CPC分类号： H03H17/0628

摘要： An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses. A coefficient calculation circuit calculates filter coefficients for the interpolation and resampling circuit in response to the difference signal.

摘要翻译： 异步采样率转换器对数字音频输入信号进行内插和滤波，以产生经过滤波的上采样的第一信号。 FIFO存储器接收第一信号并将其样本存储在由写地址确定的位置处，并且从由读地址确定的位置呈现存储的样本。 所呈现的样本通过内插和重采样电路以产生连续时间信号，该连续时间信号被重新采样以产生相对于期望输出被上采样的信号。 然后对该信号进行滤波和下采样以产生输出信号。 采样率估计电路计算表示接收音频输入信号的数据采样的时间和需要相应音频输出采样的时间的差信号，地址产生电路产生读和写地址。 系数计算电路响应于差分信号来计算内插和重采样电路的滤波器系数。

公开(公告)号：US06747858B1

公开(公告)日：2004-06-08

申请号：US10335085

申请日：2002-12-31

申请人： Terry L. Sculley ,  Xianggang Yu

发明人： Terry L. Sculley ,  Xianggang Yu

IPC分类号： H03M700

CPC分类号： H03H17/0621 ,  H03H17/0223

摘要： A digital sample rate converter converts a digital input signal (Din) having a first sample rate (Fs_in) to a corresponding digital output signal Dout having a second sample rate (Fs_out), wherein an upsampling circuit (3) upsamples the digital input signal (Din) by a factor of N and a feedback algorithm circuit (23A) receives a corresponding digital signal of the same sample rate (Fs_in*N) to produce a digital signal (X6) having a sample rate which is a second predetermined factor (M) times the second sample rate (Fs_out). That signal is filtered by a decimation filter (17) and then downsampled by a predetermined factor to produce the digital output signal (Dout) with the second sample rate (Fs_out).

摘要翻译： 数字采样率转换器将具有第一采样率（Fs_in）的数字输入信号（Din）转换为具有第二采样率（Fs_out）的对应数字输出信号Dout，其中上采样电路（3）对数字输入信号 Din），并且反馈算法电路（23A）接收相同采样率（Fs_in * N）的相应数字信号，以产生具有作为第二预定因子（M）的采样率的数字信号（X6） ）乘以第二采样率（Fs_out）。 该信号由抽取滤波器（17）滤波，然后用预定因子进行下采样，以产生具有第二采样率（Fs_out）的数字输出信号（Dout）。

公开(公告)号：US06518899B2

公开(公告)日：2003-02-11

申请号：US09978139

申请日：2001-10-15

申请人： Xianggang Yu

发明人： Xianggang Yu

IPC分类号： H03M106

CPC分类号： H03M1/0668 ,  H03M1/74 ,  H03M3/464

摘要： An improved dynamic element matching technique for providing noise-shaping of non-linearity in data converters, such as a multi-bit digital-to-analog converter, is provided. The improved DEM technique is configured with a new method for generating the bit patterns, which permits a less complex digital DEM circuit that provides improved performance. The proposed DEM algorithm introduces a new priority calculation method in which a multi-bit quantizer can be used in an oversampled delta sigma modulator to produce an output which is converted to an output code, such as a thermometer code output. The thermometer code output can be coupled as input bits through a dynamic element matching sort block to provide an output comprising a plurality of bits. Each output bit of the dynamic element matching sort block is sampled and coupled back to each of a plurality of corresponding filters, which comprise cascaded integrators. The sort block is configured to compare the respective outputs of each filter to shuffle the input bits to generate an output such that the filter output values converge towards each other. In this way, the bit sequence on each output bit line will have the noise-shaping with the order determined by the number of integrators cascaded in the signal path of each filter. The resultant output signals can then be passed through an internal multi-bit DAC to provide an output to an analog low-pass filter to remove out-of-band noise, leaving the signal band having an improved signal-to-noise (SNR) with the non-linearity components removed.

摘要翻译： 提供了一种改进的动态元件匹配技术，用于在诸如多位数模转换器之类的数据转换器中提供非线性的噪声整形。 改进的DEM技术被配置有用于产生位模式的新方法，这允许提供改善的性能的较不复杂的数字DEM电路。 所提出的DEM算法引入了一种新的优先级计算方法，其中可以在过采样的Δ-Σ调制器中使用多比特量化器来产生被转换成诸如温度计代码输出的输出代码的输出。 温度计代码输出可以通过匹配排序块的动态元件耦合作为输入比特，以提供包括多个比特的输出。 动态元素匹配排序块的每个输出位被采样并耦合回多个对应的滤波器中的每一个，其包括级联积分器。 排序块被配置为比较每个滤波器的各个输出以混洗输入比特以生成输出，使得滤波器输出值彼此会聚。 以这种方式，每个输出位线上的位序列将具有由在每个滤波器的信号路径中级联的积分器的数量确定的顺序的噪声整形。 然后，所得到的输出信号可以通过内部多位DAC，以向模拟低通滤波器提供输出以去除带外噪声，使信号频带具有改进的信噪比（SNR） 非线性元件被去除。

公开(公告)号：US6041339A

公开(公告)日：2000-03-21

申请号：US49604

申请日：1998-03-27

申请人： Xianggang Yu ,  Terry Lee Sculley ,  Jeffrey Alan Niehaus

发明人： Xianggang Yu ,  Terry Lee Sculley ,  Jeffrey Alan Niehaus

IPC分类号： H03H17/06 ,  G06F17/10

CPC分类号： H03H17/0664 ,  H03H17/0685

摘要： A decimation filtering circuit for performing a decimation operation with a decimation factor of M in a pipelined structure. A finite impulse response ("FIR") filtering of N taps for achieving a desired frequency response is designed to have an integral ratio of N/M. A total of N/M processing stages is connected in series to accumulate filtered data based on data samples of an input signal and predetermined FIR coefficients. Each of the N/M processing stages produces an accumulated output in every other M accumulations for M input data samples.

摘要翻译： 一种抽取滤波电路，用于在流水线结构中以抽取因子M执行抽取操作。 用于实现所需频率响应的N个抽头的有限脉冲响应（“FIR”）滤波被设计为具有N / M的整数比。 总共N / M个处理级串联连接，以基于输入信号和预定FIR系数的数据采样来累积滤波数据。 每个N / M处理级在M个输入数据样本的每隔一个M个累加中产生累积输出。