公开(公告)号：US07913144B2

公开(公告)日：2011-03-22

申请号：US12513401

申请日：2007-10-24

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G06F11/00

CPC分类号： G01R31/31705 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/318392

摘要： Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element 5 and a symbol injection part for a passive element 7, an occurrence probability providing part 9, an equal occurrence probability providing part 11, and a switching part 13. A per-test X-fault diagnosis flow by the diagnostic device 1 consists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element 7, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution. Since, by the occurrence probability providing part 9, a new diagnosis value is used and, the occurrence probabilities of possible faulty logic combinations are taken into consideration, the reality in a deep-submicron LSI circuit is better reflected, which contributes to the improvement of diagnostic resolution.

摘要翻译： 通过进一步提高诊断分辨率，提供诊断装置等提供有利的诊断结果。 诊断装置1具有符号注入部3，其由有源元件5的符号注入部和无源元7的符号注入部，发生概率提供部9，等发生概率提供部11， 以及切换部13.诊断装置1的每个测试X故障诊断流程包括用于收集诊断信息的阶段和用于绘制诊断结论的阶段。 深亚微米LSI电路的布局通常需要涉及多层，这意味着通孔被广泛使用。 由于无源元件7的符号注入部使用通孔信息，因此可以将缺陷定位到通孔电平，大大提高诊断分辨率。 由于通过发生概率提供部9使用新的诊断值，并且考虑了可能的故障逻辑组合的发生概率，所以更好地反映了深亚微米LSI电路中的现实，这有助于改善 诊断分辨率。

公开(公告)号：US20090019327A1

公开(公告)日：2009-01-15

申请号：US12235628

申请日：2008-09-23

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318544 ,  G01R31/318502

摘要： A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus 200 generating an initial test vector set 216 for a logic circuit includes a target vector identification unit 204 identifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set 216, and a test vector set conversion unit 206 converting the test vector identified by the test vector identification unit 204 and to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.

摘要翻译： 提供了一种用于生成能够减少在扫描捕获之前和之后产生的逻辑值中的差异的测试向量集的生成装置等，用于从全扫描时序电路中包括的扫描单元的输出。 生成用于逻辑电路的初始测试向量集合216的生成装置200包括：目标矢量识别单元204，其识别满足预定标准的测试向量，并且对于其逻辑值不同的位数（位数转换的数量）来选择 相对于包括在顺序电路中的扫描单元的输出，从初始测试向量集合216的测试向量中的扫描捕获之前和之后，以及转换由测试向量识别单元204识别的测试向量的测试向量集合转换单元206 并且被选择为减少相对于包括在顺序电路中的扫描单元的输出的位转换的数量。

公开(公告)号：US07979765B2

公开(公告)日：2011-07-12

申请号：US12442996

申请日：2007-09-25

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/10 ,  G01R31/31721 ,  G01R31/31813 ,  G01R31/31917 ,  G11C29/56004

摘要： Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device 100 generates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube. The generation device 100 includes a selection unit 101 for selecting, among the plurality of X-bits, a target X-bit, which is a target of assigning a logic value, a capture transition metric calculation unit 103 for calculating capture transition metric caused by a test cube including an X-bit, and a logic value assignment unit 105 for assigning, to the selected target X-bit, a logic value which causes the smaller capture transition metric, by applying the capture transition metric calculation means to a first test cube obtained by assigning a logic value 0 to the selected target X-bit and to a second test cube obtained by assigning a logic value 1 to the selected target X-bit, and by comparing a capture transition metric caused by a first test cube and a capture transition metric caused by a second test cube.

摘要翻译： 提供了用于生成能够有效地降低捕获功率的测试向量的生成装置等。 生成装置100通过向包括在测试立方体中的多个未指定位（X位）中的每一个分配逻辑值来生成用于逻辑电路的测试向量。 生成装置100包括：选择单元101，用于在多个X位中选择作为分配逻辑值的目标的目标X位;捕获转移度量计算单元103，用于计算由 包括X位的测试立方体和用于通过将捕获转移度量计算装置应用于第一测试来向所选择的目标X位分配导致较小捕获转换度量的逻辑值的逻辑值分配单元105 通过将逻辑值0分配给所选择的目标X位获得的立方体以及通过将逻辑值1分配给所选择的目标X位获得的第二测试立方体，并且通过将由第一测试立方体引起的捕获转变度量与 由第二个测试立方体引起的捕获转换度量。

公开(公告)号：US07962822B2

公开(公告)日：2011-06-14

申请号：US12235628

申请日：2008-09-23

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318502

摘要： A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus 200 generating an initial test vector set 216 for a logic circuit includes a target vector identification unit 204 identifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set 216, and a test vector set conversion unit 206 converting the test vector identified by the test vector identification unit 204 and to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.

摘要翻译： 提供了一种用于生成能够减少在扫描捕获之前和之后产生的逻辑值中的差异的测试向量集的生成装置等，用于从全扫描时序电路中包括的扫描单元的输出。 生成用于逻辑电路的初始测试向量集合216的生成装置200包括：目标矢量识别单元204，其识别满足预定标准的测试向量，并且对于其逻辑值不同的位数（位数转换的数量）来选择 相对于包括在顺序电路中的扫描单元的输出，从初始测试向量集合216的测试向量中的扫描捕获之前和之后，以及转换由测试向量识别单元204识别的测试向量的测试向量集合转换单元206 并且被选择为减少相对于包括在顺序电路中的扫描单元的输出的位转换的数量。

公开(公告)号：US20090319842A1

公开(公告)日：2009-12-24

申请号：US12442996

申请日：2007-09-25

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G06F11/25 ,  G01R31/28

CPC分类号： G11C29/10 ,  G01R31/31721 ,  G01R31/31813 ,  G01R31/31917 ,  G11C29/56004

摘要： Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device 100 generates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube. The generation device 100 includes a selection unit 101 for selecting, among the plurality of X-bits, a target X-bit, which is a target of assigning a logic value, a capture transition metric calculation unit 103 for calculating capture transition metric caused by a test cube including an X-bit, and a logic value assignment unit 105 for assigning, to the selected target X-bit, a logic value which causes the smaller capture transition metric, by applying the capture transition metric calculation means to a first test cube obtained by assigning a logic value 0 to the selected target X-bit and to a second test cube obtained by assigning a logic value 1 to the selected target X-bit, and by comparing a capture transition metric caused by a first test cube and a capture transition metric caused by a second test cube.

摘要翻译： 提供了用于生成能够有效地降低捕获功率的测试向量的生成装置等。 生成装置100通过向包括在测试立方体中的多个未指定位（X位）中的每一个分配逻辑值来生成用于逻辑电路的测试向量。 生成装置100包括：选择单元101，用于在多个X位中选择作为分配逻辑值的目标的目标X位;捕获转移度量计算单元103，用于计算由 包括X位的测试立方体和用于通过将捕获转移度量计算装置应用于第一测试来向所选择的目标X位分配导致较小捕获转换度量的逻辑值的逻辑值分配单元105 通过将逻辑值0分配给所选择的目标X位获得的立方体以及通过将逻辑值1分配给所选择的目标X位获得的第二测试立方体，并且通过将由第一测试立方体引起的捕获转变度量与 由第二个测试立方体引起的捕获转换度量。

公开(公告)号：US20100064191A1

公开(公告)日：2010-03-11

申请号：US12513401

申请日：2007-10-24

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31705 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/318392

摘要： Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element 5 and a symbol injection part for a passive element 7, an occurrence probability providing part 9, an equal occurrence probability providing part 11, and a switching part 13. A per-test X-fault diagnosis flow by the diagnostic device 1 consists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element 7, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution. Since, by the occurrence probability providing part 9, a new diagnosis value is used and, the occurrence probabilities of possible faulty logic combinations are taken into consideration, the reality in a deep-submicron LSI circuit is better reflected, which contributes to the improvement of diagnostic resolution.

摘要翻译： 通过进一步提高诊断分辨率，提供诊断装置等提供有利的诊断结果。 诊断装置1具有符号注入部3，其由有源元件5的符号注入部和无源元7的符号注入部，发生概率提供部9，等发生概率提供部11， 以及切换部13.诊断装置1的每个测试X故障诊断流程包括用于收集诊断信息的阶段和用于绘制诊断结论的阶段。 深亚微米LSI电路的布局通常需要涉及多层，这意味着通孔被广泛使用。 由于无源元件7的符号注入部使用通孔信息，因此可以将缺陷定位到通孔电平，大大提高诊断分辨率。 由于通过发生概率提供部9使用新的诊断值，并且考虑了可能的故障逻辑组合的发生概率，所以更好地反映了深亚微米LSI电路中的现实，这有助于改善 诊断分辨率。

公开(公告)号：US07971118B2

公开(公告)日：2011-06-28

申请号：US12129746

申请日：2008-05-30

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318547 ,  G01R31/318335 ,  G01R31/318502

摘要： Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vector set corresponding to the full scan sequential circuit. The conversion device comprises a setting unit for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit.

摘要翻译： 提供了一种转换装置和其他用于转换测试矢量集，以便减少在全扫描时序电路中包括的扫描单元的输出中扫描捕获之前和之后产生的逻辑值差。 转换装置转换对应于全扫描时序电路的测试矢量集。 转换装置包括：设置单元，用于根据预定的约束条件，基于逻辑电路中的输入 - 输出关系设置可以是无关位的候选比特和不能不关心比特的固定比特 为了识别不关心的位，可以从测试向量集合的每个测试向量不关心，以及逻辑值决定单元，用于根据关系中的关系来确定无关位的逻辑值 相对于包括由设置单元标识的无关位的测试立方体的多个位对。

公开(公告)号：US20080235543A1

公开(公告)日：2008-09-25

申请号：US12129746

申请日：2008-05-30

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318547 ,  G01R31/318335 ,  G01R31/318502

摘要： Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device 400 converts a test vector set corresponding to the full scan sequential circuit. The conversion device 400 comprises a setting unit 402 for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit 404 for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit 402.

摘要翻译： 提供了一种转换装置和其他用于转换测试矢量集，以便减少在全扫描时序电路中包括的扫描单元的输出中扫描捕获之前和之后产生的逻辑值差。 转换装置400转换对应于全扫描时序电路的测试矢量集。 转换装置400包括：设置单元402，用于根据预定约束条件，基于输入输出关系设置可以是无关位的候选比特和不能为无关位的固定比特 逻辑电路，以便识别不考虑位置的每个测试向量集合中的每个测试矢量都不需要关心的位;以及逻辑值判定单元404，用于根据以下内容确定无关位的逻辑值： 关于包括由设置单元402识别的无关位的测试立方体的多个比特对中的关系。

公开(公告)号：US20090113261A1

公开(公告)日：2009-04-30

申请号：US12345310

申请日：2008-12-29

申请人： Seiji Kajihara ,  Kohei Miyase ,  Xiaqing Wen ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Seiji Kajihara ,  Kohei Miyase ,  Xiaqing Wen ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318328 ,  G01R31/318335

摘要： Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern 100a given in advance for a logic circuit into an intermediate test pattern 100b of a bit constitution of different logic values, where the constitution elements of the initial test pattern 100a are at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test pattern 100a which meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.

摘要翻译： 提供了一种用于将预先给出的初始测试图案转换成不同逻辑值的比特构造的测试图案的转换装置等，而不会丢失可由初始化的构成元素检测到的过渡延迟故障的故障覆盖 测试模式。 转换装置将用于逻辑电路的预先给出的初始测试图案100a转换成不同逻辑值的比特结构的中间测试图案100b，其中初始测试图案100a的构成元素是连续应用的至少两个测试矢量 。 转换装置包括判定装置，用于决定初始测试图案100a中的逻辑值的组合，其满足通过应用构成要素可以检测的逻辑电路的故障的检测条件。

公开(公告)号：US08037387B2

公开(公告)日：2011-10-11

申请号：US12345310

申请日：2008-12-29

申请人： Seiji Kajihara ,  Kohei Miyase ,  Xiaqing Wen ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Seiji Kajihara ,  Kohei Miyase ,  Xiaqing Wen ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G06F11/00

CPC分类号： G01R31/318328 ,  G01R31/318335

摘要： Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern 100a given in advance for a logic circuit into an intermediate test pattern 100b of a bit constitution of different logic values, where the constitution elements of the initial test pattern 100a are at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test pattern 100a which meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.

摘要翻译： 提供了一种用于将预先给出的初始测试图案转换成不同逻辑值的比特构造的测试图案的转换装置等，而不会丢失可由初始化的构成元素检测到的过渡延迟故障的故障覆盖 测试模式。 转换装置将用于逻辑电路的预先给出的初始测试图案100a转换成不同逻辑值的比特结构的中间测试图案100b，其中初始测试图案100a的构成元素是连续应用的至少两个测试矢量 。 转换装置包括判定装置，用于决定初始测试图案100a中的逻辑值的组合，其满足通过应用构成要素可以检测的逻辑电路的故障的检测条件。