公开(公告)号：US11082067B1

公开(公告)日：2021-08-03

申请号：US16592381

申请日：2019-10-03

Applicant: XILINX, INC.

Inventor： Ming Ruan ,  Gordon I. Old ,  Richard L. Walke ,  Zahid Khan

IPC: H03M13/13 ,  G06F1/03 ,  G06F9/30 ,  H03M13/09

Abstract: Embodiments described herein provide a code generation mechanism (FIG. 3, 301) in a Polar encoder (FIG. 2, 204) to determine a bit type (FIG. 3, 312) corresponding to each coded bit in the Polar code before sending the data bits for encoding (FIG. 3, 303). For example, each bit in the Polar code is determined to have a bit type of a frozen bit, parity bit, an information bit, or a cyclic redundancy check (CRC) bit based at least on the respective reliability index of the bit from a pre-computed reliability index lookup table (FIG. 4A, 411). In this way, the bit type determination can be completed in one loop by iterating the list of entries in the pre-computed reliability index lookup table.

公开(公告)号：US11206045B1

公开(公告)日：2021-12-21

申请号：US16937253

申请日：2020-07-23

Applicant: Xilinx, Inc.

Inventor： Zahid Khan

IPC: H03M13/13 ,  H03M13/09

Abstract: An apparatus for determining a bit index for a parity bit of a polar codeword is disclosed. Each index of a polar codeword may have an associated weight and an associated reliability value. The apparatus may compare the weights and reliability values of a group of bit indices in parallel to determine a bit index of the group associated with the lowest weight and highest reliability value. Additional groups may be processed until all of the bit indices of the polar codeword have been examined and the bit index with the lowest weight and highest reliability value is identified.

公开(公告)号：US10833704B1

公开(公告)日：2020-11-10

申请号：US16217648

申请日：2018-12-12

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Andrew Dow ,  Zahid Khan

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/37 ,  G06F11/10

Abstract: Low-density parity check (LDPC) decoder circuitry is configured to decode an input codeword using a plurality of circulant matrices of a parity check matrix for an LDPC code. Multiple memory banks are configured to store elements of the input codeword. A memory circuit is configured for storage of an instruction sequence. Each instruction describes for one of the circulant matrices, a corresponding layer and column of the parity check matrix and a rotation. Each instruction includes packing factor bits having a value indicative of a number of instructions of the instruction sequence to be assembled in a bundle of instructions. A bundler circuit is configured to assemble the number of instructions from the memory circuit in a bundle. The bundler circuit specifies one or more no-operation codes (NOPs) in the bundle in response to the value of the packing factor bits and provides the bundle to the decoder circuitry.