公开(公告)号：US11455369B1

公开(公告)日：2022-09-27

申请号：US17169072

申请日：2021-02-05

Applicant: XILINX, INC.

Inventor： Andrew Whyte

IPC: G06F17/14

Abstract: Embodiments herein describe an FFT that can bypass one or more stages when processing smaller frames. For example, when all the stages in the FFT are active, the FFT can process up to a maximum supported point size. However, the particular application may only every send smaller sized frames to the FFT. Instead of unnecessarily passing these frames through the beginning stages of the FFT (which adds latency and consumes power), the embodiments herein can bypass the unneeded stages which reduces the maximum point size the FFT can process but saves power and reduces latency. For example, the FFT can have selection circuitry (e.g., multiplexers) disposed between each stage that permits the input data to either bypass the previous stage(s) or the subsequent stage(s), depending on the architecture of the FFT. The bypassed stages can then be deactivated to conserve power.

公开(公告)号：US09244885B1

公开(公告)日：2016-01-26

申请号：US13837050

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Gordon I. Old ,  Andrew Whyte

IPC: G06F17/10

CPC classification number: G06F1/0328

Abstract: An apparatus relating generally to accumulation is disclosed. In this apparatus, a first subtraction-bypass stage is coupled to receive an input operand and a modulus operand to provide a first difference and the input operand. An accumulation stage is coupled to the first subtraction-bypass stage to receive the first difference and the input operand. The accumulation stage is coupled to receive an offset operand for providing an offset-accumulated result. A second subtraction-bypass stage is coupled to receive the offset operand and the modulus operand to provide a second difference and the offset operand. A consolidation stage is coupled to receive the offset operand, the second difference and the offset-accumulated result to provide a consolidated accumulated result. The first subtraction-bypass stage, the accumulation stage, the second subtraction-bypass stage, and the consolidation stage are for a redundant number system.

Abstract translation: 公开了一般涉及积累的装置。 在该装置中，第一减法旁路级被耦合以接收输入操作数和模数操作数以提供第一差值和输入操作数。 累积级耦合到第一减法旁路级以接收第一差值和输入操作数。 累加阶段被耦合以接收用于提供偏移累积结果的偏移操作数。 耦合第二减法旁路级以接收偏移操作数和模数操作数以提供第二差值和偏移操作数。 耦合整合级以接收偏移操作数，第二差和偏移累加结果以提供合并累积结果。 第一减法旁路级，累积级，第二减法旁路级和合并级用于冗余数字系统。