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公开(公告)号：US10727873B1
公开(公告)日：2020-07-28
申请号：US16373434
申请日：2019-04-02
Applicant: Xilinx, Inc.
Inventor： Gordon I. Old
Abstract: A decoder circuit includes an input configured to receive an encoded message, and a decoding loop circuit including first and second memories, an update circuit, and a sort circuit. The decoding loop circuit is configured to perform list decoding to the encoded message by successively decoding a plurality of bits of a first codeword of the encoded message in a plurality of decoding loops respectively; and provide, to an output, a decoded message. In each decoding loop, the update circuit is configured to receive, from the first memory, parent path values, and provide, to a second memory, child path values based on the parent path values. The sort circuit is configured to receive, from the second memory, the child path values; and provide, to the first memory, surviving child path values based on the child path values.
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公开(公告)号：US10831231B1
公开(公告)日：2020-11-10
申请号：US15939255
申请日：2018-03-28
Applicant: Xilinx, Inc.
Inventor： Gordon I. Old
Abstract: A circuit for implementing a polar decoder is described. The circuit includes a log-likelihood ratio processing circuit. A path metric update circuit is coupled to receive log-likelihood values for decoded bits from the log-likelihood ratio processing circuit, wherein the path metric circuit generates path metric values for the decoded bits. A partial sum calculation circuit is coupled to receive the path metrics; and a sort and cull circuit is coupled to receive a list of child path, wherein the sort and cull circuit eliminates invalid paths from the list of child paths. A method of implementing a polar decoder is also described.
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公开(公告)号：US11082067B1
公开(公告)日：2021-08-03
申请号：US16592381
申请日：2019-10-03
Applicant: XILINX, INC.
Inventor： Ming Ruan , Gordon I. Old , Richard L. Walke , Zahid Khan
Abstract: Embodiments described herein provide a code generation mechanism (FIG. 3, 301) in a Polar encoder (FIG. 2, 204) to determine a bit type (FIG. 3, 312) corresponding to each coded bit in the Polar code before sending the data bits for encoding (FIG. 3, 303). For example, each bit in the Polar code is determined to have a bit type of a frozen bit, parity bit, an information bit, or a cyclic redundancy check (CRC) bit based at least on the respective reliability index of the bit from a pre-computed reliability index lookup table (FIG. 4A, 411). In this way, the bit type determination can be completed in one loop by iterating the list of entries in the pre-computed reliability index lookup table.
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Patent Agency Ranking
公开(公告)号：US10659083B1
公开(公告)日：2020-05-19
申请号：US16150142
申请日：2018-10-02
Applicant: Xilinx, Inc.
Inventor： Gordon I. Old , Justin A. Fritz
Abstract: Apparatuses and methods generally relating to a sort system, such as may be used in a data processing kernel, for list decoding of a Polar codeword are described. In one such sort system, a sorter circuit is configured to receive and sort path metrics for coded bits of the Polar codeword. The path metrics are obtained from log-likelihood ratios associated with the coded bits. A limiter circuit is configured to cull the sorted path metrics to provide a list having a subset of the path metrics to limit output paths of a list decoder. A normalizer circuit is configured to subtract a path metric of the path metrics or a threshold metric representing a minimum metric respectively from entries in the list to provide normalized path metrics to decode the Polar codeword.
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公开(公告)号：US10484021B1
公开(公告)日：2019-11-19
申请号：US15916090
申请日：2018-03-08
Applicant: Xilinx, Inc.
Inventor： Gordon I. Old , Richard L. Walke
Abstract: Apparatuses and methods relating generally to a decoder. In an apparatus, a control circuit receives first-third sign signals, a partial sum signal, a function select signal, and a carry signal as an input vector to provide an output sign and a vector select. A select generation circuit receives the first and second sign signals and the partial sum signal to provide an add/subtract select signal. A subtractor subtracts from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal. Responsive to the add/subtract select signal, an adder/subtractor either adds or subtracts the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal. A multiplexer selects from the first and second absolute value signals, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select.
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6.发明授权公开(公告)号：US10713013B1
公开(公告)日：2020-07-14
申请号：US15052564
申请日：2016-02-24
Applicant: Xilinx, Inc.
Inventor： Gordon I. Old
Abstract: An apparatus for an exponential function for a half-precision floating-point format for an exponent x includes a denormalizer for receiving sign, exponent and significand bits for conversion of significant bits to a fixed-point format for a signed fixed-point representation. A splicer receives the signed fixed-point representation to output first, second and third splices. A first lookup table receives the first splice for accessing a floating-point exponent and a floating-point mantissa. A second lookup table receives the second splice for accessing a fixed-point exponent value. A first multiplier receives the fixed-point exponent value and the third splice to provide a first multiplication result. An adder receives the fixed-point exponent value and the first multiplication result to provide a sum. A second multiplier receives the floating-point mantissa and the sum to provide a second multiplication result. A combination of the floating-point exponent and the second multiplication result is a floating-point value.
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公开(公告)号：US10700709B1
公开(公告)日：2020-06-30
申请号：US15965271
申请日：2018-04-27
Applicant: Xilinx, Inc.
Inventor： Gordon I. Old
Abstract: Apparatus and method relates generally to data processing kernel. In such an apparatus, a datapath pipeline is configured to process datasets interlaced with respect to one another for multiple passes through a loop with conditional or data dependent decision points. A queue manager is configured with control circuitry sets to provide an instruction interface to the datapath pipeline. Each of the control circuitry sets includes: a first buffer and a second buffer each configured to buffer tokens for correspondence with the datasets. Each of the control circuitry sets further includes: an arbiter configured to decouple the conditional or data dependent decision points from the datapath pipeline to selectively provide access of the first buffer or the second buffer to the datapath functions. Memory is configured to provide access to and storage of the datasets to the datapath pipeline.
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公开(公告)号：US09244885B1
公开(公告)日：2016-01-26
申请号：US13837050
申请日：2013-03-15
Applicant: Xilinx, Inc.
Inventor： Gordon I. Old , Andrew Whyte
IPC: G06F17/10
CPC classification number: G06F1/0328
Abstract: An apparatus relating generally to accumulation is disclosed. In this apparatus, a first subtraction-bypass stage is coupled to receive an input operand and a modulus operand to provide a first difference and the input operand. An accumulation stage is coupled to the first subtraction-bypass stage to receive the first difference and the input operand. The accumulation stage is coupled to receive an offset operand for providing an offset-accumulated result. A second subtraction-bypass stage is coupled to receive the offset operand and the modulus operand to provide a second difference and the offset operand. A consolidation stage is coupled to receive the offset operand, the second difference and the offset-accumulated result to provide a consolidated accumulated result. The first subtraction-bypass stage, the accumulation stage, the second subtraction-bypass stage, and the consolidation stage are for a redundant number system.
Abstract translation: 公开了一般涉及积累的装置。 在该装置中，第一减法旁路级被耦合以接收输入操作数和模数操作数以提供第一差值和输入操作数。 累积级耦合到第一减法旁路级以接收第一差值和输入操作数。 累加阶段被耦合以接收用于提供偏移累积结果的偏移操作数。 耦合第二减法旁路级以接收偏移操作数和模数操作数以提供第二差值和偏移操作数。 耦合整合级以接收偏移操作数，第二差和偏移累加结果以提供合并累积结果。 第一减法旁路级，累积级，第二减法旁路级和合并级用于冗余数字系统。
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