中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.011 seconds)

    Predictive circuit design for integrated circuits
    2.
    发明授权
    Predictive circuit design for integrated circuits 有权

    公开(公告)号：US09881117B1

    公开(公告)日：2018-01-30

    申请号：US15204883

    申请日：2016-07-07

    Applicant: Xilinx, Inc.

    Inventor： Anindita Patra ,  Nabeel Shirazi

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5068

    Abstract: A method for creating a circuit design for an integrated circuit includes, responsive to a request to modify a current circuit design, determining, using a processor, a first core used in the current circuit design and predicting, using the processor, a second core not yet included in the current circuit design as a candidate core for inclusion in the current circuit design. The second core is determined based upon usage of the second core and the first core, in combination, in a plurality of example circuit designs.

    System and method for preparing partially reconfigurable circuit designs
    3.
    发明授权
    System and method for preparing partially reconfigurable circuit designs 有权
    用于制备部分可重构电路设计的系统和方法

    公开(公告)号：US09183339B1

    公开(公告)日：2015-11-10

    申请号：US14538595

    申请日：2014-11-11

    Applicant: Xilinx, Inc.

    Inventor： Nabeel Shirazi ,  David Robinson ,  Amit Kasat ,  Arvind Sundararajan

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F17/505

    Abstract: A circuit design is created in a computer memory in response to user input to a computer processor. The circuit design has a static portion. A virtual socket is instantiated in the circuit design in response to user input, and one or more reconfigurable modules are instantiated in the virtual socket in response to user input. The static portion of the circuit design is coupled to the one or more reconfigurable modules, and configuration data are generated from the circuit design. The configuration data include a configuration bitstream corresponding to the static portion of the circuit design and one or more partial configuration bitstreams corresponding to the one or more reconfigurable modules.

    Abstract translation: 响应于用户对计算机处理器的输入，在计算机存储器中创建电路设计。 电路设计有静态部分。 响应于用户输入，在电路设计中实例化虚拟插座，并且响应于用户输入在虚拟插座中实例化一个或多个可重新配置的模块。 电路设计的静态部分耦合到一个或多个可重新配置的模块，并且从电路设计产生配置数据。 配置数据包括对应于电路设计的静态部分的配置比特流和对应于一个或多个可重新配置模块的一个或多个部分配置比特流。

    System level circuit design
    4.
    发明授权
    System level circuit design 有权
    系统级电路设计

    公开(公告)号：US08769449B1

    公开(公告)日：2014-07-01

    申请号：US13763317

    申请日：2013-02-08

    Applicant: Xilinx, Inc.

    Inventor： Adam P. Donlin ,  Biping Wu ,  Kyle Corbett ,  Nabeel Shirazi ,  Shay P. Seng ,  Amit Kasat ,  Srinivas Beeravolu ,  Khang K. Dao ,  Jeffrey H. Seltzer ,  Christopher J. Case

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F2217/66

    Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

    Abstract translation: 公开了用于产生电路设计的方法。 响应于用户输入，在电路设计中实例化多个单元。 每个单元的接口参数的集合被布置成如由与该单元相对应的接口模型所指示的接口层级。 对于每个接口级别，包括在接口级别中的单元的接口参数的集合的值分别传播到直接连接到该单元的其他单元。 响应于将接口参数的值从多个小区的另一小区传播到小区，并且具有与传播值不同的对应接口参数的小区的小区响应于小区的对应接口参数的值 使用与对应的接口电平相关联的相应传播函数来确定。

    Circuit design simulation
    5.
    发明授权
    Circuit design simulation 有权
    电路设计仿真

    公开(公告)号：US08769448B1

    公开(公告)日：2014-07-01

    申请号：US13747940

    申请日：2013-01-23

    Applicant: Xilinx, Inc.

    Inventor： Arvind Sundararajan ,  Nabeel Shirazi ,  Sean P. Caffee

    IPC: G06F17/50

    CPC classification number: G06F17/5022

    Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.

    Abstract translation: 在一个实施例中，提供了一种用于处理电路设计的方法，该电路设计具有配置成耦合到硬件平台上的设备的相应第一和第二组端口的第一和第二组端口。 在数据采集模式下，使用用户可选择的插件来模拟电路设计，该插件将电路设计的端口耦合到接口电路。 在仿真期间，接口电路在电路设计的各个端口和设备的端口之间传送数据。 在部署模式中，电路设计在硬件平台中实现，其中电路设计的第一和第二组端口分别耦合到设备的第一和第二组端口。

Patent Agency Ranking