公开(公告)号：US20030071653A1

公开(公告)日：2003-04-17

申请号：US10295713

申请日：2002-11-15

申请人： Xilinx, Inc.

发明人： Richard A. Carberry ,  Barbara Dahl ,  Steven P. Young ,  Trevor J. Bauer

IPC分类号： H03K019/177

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.

摘要翻译： 用于可编程逻辑器件（PLD）的快速，节省空间的查找表（LUT），其中修改LUT的写解码器，读取解码器和存储器块以提供高性能，同时提供高效布局。 写解码器和读取解码器都由LUT输入信号控制，数据信号被直接发送到存储器块的每个存储电路（即不经过写入解码器）。 读取解码器包括由一系列多路复用器组成的复用电路，该多路复用器由从PLD的互连资源接收的输入信号直接控制。 在一个实施例中，可配置逻辑块被提供有由第一LUT和第二LUT共享的单个写入解码器。