公开(公告)号：US10823780B1

公开(公告)日：2020-11-03

申请号：US16112433

申请日：2018-08-24

Applicant: Xilinx, Inc.

Inventor： Andrew Tabalujan ,  Xiaobao Wang ,  Gubo Huang

IPC: G01R31/28 ,  G01R19/257 ,  H04B17/20 ,  H01L25/065

Abstract: Examples herein describe techniques for testing a receiver interface on a die. In one embodiment, the die includes tester circuitry which includes a digital to analog convertor (DAC) which outputs an analog test signal to a selector circuit (e.g., a multiplexer) which forwards the analog test signal to a receiver. By varying the analog test signal, the tester circuitry can identify one or more trip points corresponding to the receiver. That is, by monitoring the output of the receiver, a testing application can determine when the output of the receiver switches states thereby indicating that the analog test signal at the input of the receiver corresponds to the trip point of the receiver. In this manner, internal circuitry (e.g., the tester circuitry) can be used to test a receiver interface that may otherwise be inaccessible.

公开(公告)号：US10656202B1

公开(公告)日：2020-05-19

申请号：US16137888

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Sing-Keng Tan ,  Xiaobao Wang ,  Andrew Tabalujan ,  Gubo Huang

IPC: G01R31/317 ,  G01R31/3185

Abstract: Examples of the present disclosure provide example devices that include an integrated circuit that has debugging capability. In some examples, a device includes an integrated circuit die. The integrated circuit die includes an input/output (IO) base cell and a debug port. The IO base cell has an interface node and a feedback node. The interface node is configured to be coupled to memory, such as via an interposer, for communication therebetween. The IO base cell is configurable to selectively output to the feedback node a signal that is on the interface node. The debug port has an input node and an output node. The input node is electrically connected to the feedback node. The debug port is configurable to selectively output to the output node a signal that is on the input node. The output node is configured to be coupled to a pin exterior to the integrated circuit die.

公开(公告)号：US20160056823A1

公开(公告)日：2016-02-25

申请号：US14466569

申请日：2014-08-22

Applicant: Xilinx, Inc.

Inventor： Fu-Hing Ho ,  Gubo Huang

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/017581 ,  H03K19/0185

Abstract: In an example implementation, a level-shifter circuit in an integrated circuit (IC) includes a plurality field-effect transistors (FETs) coupled to provide: a first inverter having an input port configured to receive an input signal having a first supply voltage, an output port, and a bias port; a second inverter having an input port coupled to the output port of the first inverter, an output port, and a bias port coupled to a second supply voltage; a diode-connected FET coupled between the second supply voltage and the bias port of the first inverter; a first FET in parallel with the diode-connected FET having a gate coupled to the output of the second inverter; and a second FET in parallel with the diode-connected FET and the first FET having a gate configured to receive a mode select signal.

Abstract translation: 在示例实现中，集成电路（IC）中的电平移动器电路包括多个场效应晶体管（FET），其耦合以提供：第一反相器，其具有被配置为接收具有第一电源电压的输入信号的输入端口， 输出端口和偏置端口; 第二反相器具有耦合到第一反相器的输出端口的输入端口，输出端口和耦合到第二电源电压的偏置端口; 耦合在第二电源电压和第一反相器的偏置端口之间的二极管连接的FET; 与二极管连接的FET并联的第一FET，具有耦合到第二反相器的输出端的栅极; 以及与二极管连接的FET并联的第二FET和具有配置为接收模式选择信号的栅极的第一FET。

公开(公告)号：US10530324B1

公开(公告)日：2020-01-07

申请号：US16107117

申请日：2018-08-21

Applicant: Xilinx, Inc.

Inventor： Gubo Huang ,  Xiaobao Wang ,  Andrew Tabalujan ,  Sing-Keng Tan

IPC: H03H7/38 ,  G01R27/14 ,  H01L23/00 ,  H01L25/18 ,  G11C7/10 ,  G11C5/06

Abstract: Examples herein describe a die that includes a testing system (e.g., testing circuitry) for measuring the actual resistance of on-die resistors. When testing the die, an I/O element (e.g., a solder bump) can be used to sweep a voltage across the on-die resistor. The testing system identifies when the voltage across the on-die resistor reaches a predefined reference voltage and measures the corresponding current. Using the measured current and the reference voltage, the testing system can identify the actual resistance of the on-die resistor. In one embodiment, the on-die resistor is tunable such if the on-die resistor has a divergent value, the die can adjust its resistance value to the desired value.

公开(公告)号：US09407266B2

公开(公告)日：2016-08-02

申请号：US14466569

申请日：2014-08-22

Applicant: Xilinx, Inc.

Inventor： Fu-Hing Ho ,  Gubo Huang

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/017581 ,  H03K19/0185

Abstract: In an example implementation, a level-shifter circuit in an integrated circuit (IC) includes a plurality field-effect transistors (FETs) coupled to provide: a first inverter having an input port configured to receive an input signal having a first supply voltage, an output port, and a bias port; a second inverter having an input port coupled to the output port of the first inverter, an output port, and a bias port coupled to a second supply voltage; a diode-connected FET coupled between the second supply voltage and the bias port of the first inverter; a first FET in parallel with the diode-connected FET having a gate coupled to the output of the second inverter; and a second FET in parallel with the diode-connected FET and the first FET having a gate configured to receive a mode select signal.

Abstract translation: 在示例实现中，集成电路（IC）中的电平移动器电路包括多个场效应晶体管（FET），其耦合以提供：第一反相器，其具有被配置为接收具有第一电源电压的输入信号的输入端口， 输出端口和偏置端口; 第二反相器具有耦合到第一反相器的输出端口的输入端口，输出端口和耦合到第二电源电压的偏置端口; 耦合在第二电源电压和第一反相器的偏置端口之间的二极管连接的FET; 与二极管连接的FET并联的第一FET，具有耦合到第二反相器的输出端的栅极; 以及与二极管连接的FET并联的第二FET和具有配置为接收模式选择信号的栅极的第一FET。