公开(公告)号：US09501604B1

公开(公告)日：2016-11-22

申请号：US14493750

申请日：2014-09-23

Applicant: Xilinx, Inc.

Inventor： Geetesh More ,  Srinivasan Dasasathyan ,  Nagaraj Savithri

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5027 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/84

Abstract: A method of testing a circuit design includes generating, for each net of each critical path in the circuit design, a respective ring oscillator circuit design. The ring oscillator circuit design has a source gate coupled to a destination gate via the net and a feedback path that couples an output pin of the destination gate to an input pin of the source gate. Configuration data are generated to implement a respective ring oscillator circuit from each ring oscillator circuit design, and a programmable integrated circuit is configured with the configuration data. The method determines a delay of the net of each ring oscillator circuit.

Abstract translation: 一种测试电路设计的方法包括为电路设计中的每个关键路径的每个网络产生相应的环形振荡器电路设计。 环形振荡器电路设计具有经由网络耦合到目的地门的源极和将目的地门的输出引脚耦合到源极栅极的输入引脚的反馈路径。 生成配置数据以实现来自每个环形振荡器电路设计的相应环形振荡器电路，并且可编程集成电路被配置有配置数据。 该方法确定每个环形振荡器电路的网络的延迟。