公开(公告)号：US09287899B1

公开(公告)日：2016-03-15

申请号：US14137812

申请日：2013-12-20

Applicant: Xilinx, Inc.

Inventor： Raied N. Mazahreh ,  Raghavendar M. Rao ,  Krishna R. Narayanan ,  Henry D. Pfister

IPC: H03M13/27

CPC classification number: H03M13/2927 ,  H03M13/152 ,  H03M13/2921

Abstract: Methods and circuits are disclosed for forward-error-correction (FEC) decoding. A plurality of symbols are received in an interleaved format of rows and columns of the symbols. A plurality of FEC decoding iterations are performed on the plurality of symbols. Each decoding iteration performs FEC decoding of the rows of the plurality of symbols and performs FEC decoding of the columns of the plurality of symbols. After performing the decoding iterations, rows in error and columns in error of the plurality of symbols are determined. In response to the determined rows in error and the determined columns in error matching a deadlock pattern, symbols at intersections of the determined rows and columns in error are determined. Bits of one or more symbols of the determined symbols are inverted. After the inverting of the bits, one or more of the FEC decoding iterations are performed.

Abstract translation: 公开了用于前向纠错（FEC）解码的方法和电路。 以符号的行和列的交错格式接收多个符号。 对多个符号执行多个FEC解码迭代。 每个解码迭代执行多个符号的行的FEC解码，并对多个符号的列执行FEC解码。 在执行解码迭代之后，确定错误的行和多个符号的错误列。 响应于确定的错误行和确定的错误匹配死锁模式的列，确定所确定的行和错误列的交点处的符号。 所确定的符号的一个或多个符号的位被反转。 在比特反转之后，执行一个或多个FEC解码迭代。

公开(公告)号：US08959418B1

公开(公告)日：2015-02-17

申请号：US13691501

申请日：2012-11-30

Applicant: Xilinx, Inc.

Inventor： Henry D. Pfister ,  Krishna R. Narayanan ,  Raied N. Mazahreh ,  Raghavendar M. Rao

IPC: H03M13/00 ,  H03M13/05

CPC classification number: H03M13/2906 ,  H03M13/152 ,  H03M13/2921 ,  H03M13/2948

Abstract: In one embodiment, a circuit for FEC decoding includes first and second syndrome calculation circuits, configured to calculate FEC syndromes for rows and columns of symbols in a de-interleaved format, respectively. A decoding circuit is configured to arrange the symbols into windows. Each window includes a plurality of sequential rows and sequential columns of the symbols in the de-interleaved format. The decoding circuit is configured to place N of the windows in a group and perform M decoding iterations of the windows in the group. In each decoding iteration, the decoding circuit performs FEC decoding of rows of each of the windows in the group followed by FEC decoding of columns of each of the windows in the group.

Abstract translation: 在一个实施例中，用于FEC解码的电路包括第一和第二校正子计算电路，被配置为分别以解交错格式计算行和列符号的FEC校验子。 解码电路被配置为将符号布置成窗口。 每个窗口包括解交织格式的多个顺序行和符号的顺序列。 解码电路被配置为将N个窗口放置在组中，并对该组中的窗口执行M个解码迭代。 在每个解码迭代中，解码电路对组中的每个窗口的行进行FEC解码，接着对组中的每个窗口的列进行FEC解码。