公开(公告)号：US20150356027A1

公开(公告)日：2015-12-10

申请号：US14301008

申请日：2014-06-10

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  James J. Murray ,  Hyun W. Kwon ,  Nishit Patel

IPC: G06F12/14 ,  G06F13/30

CPC classification number: G06F12/145 ,  G06F13/00 ,  G06F13/28 ,  G06F13/30

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Abstract translation: 描述了一种能够访问数据的电路。 该电路包括存储具有第一预定大小的数据块的存储器件; 以及直接存储器访问电路，其耦合到所述存储器件，所述直接存储器电路访问具有大于所述第一预定大小的第二预定尺寸的数据有效载荷; 其中所述直接存储器访问电路响应于具有对应于存储在所述存储器件中的预定数量的数据块的多个地址的描述符来访问所述数据有效载荷。 还公开了一种能够访问数据的方法。

公开(公告)号：US10672098B1

公开(公告)日：2020-06-02

申请号：US15946300

申请日：2018-04-05

Applicant: Xilinx, Inc.

Inventor： Cyril Chemparathy ,  Mrinal J. Sarmah ,  Hyun W. Kwon ,  Maurice Penners

IPC: G06T1/60

Abstract: Systems and method for synchronizing access to buffered data are disclosed. In such a method, video data is buffered in a frame buffer memory by a producer device. A write level indicator is provided to a synchronizer by the producer device. A read level indicator is provided to the synchronizer by a consumer device. The synchronizer compares the write level indicator with the read level indicator to determine a difference. The consumer device is informed by the synchronizer when the difference meets a sub-frame threshold. The consumer device reads the buffered data from the frame buffer memory on a sub-frame-by-sub-frame basis responsive to the informing.

公开(公告)号：US09558129B2

公开(公告)日：2017-01-31

申请号：US14301008

申请日：2014-06-10

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  James J. Murray ,  Hyun W. Kwon ,  Nishit Patel

IPC: G06F13/00 ,  G06F12/14 ,  G06F13/30 ,  G06F13/28

CPC classification number: G06F12/145 ,  G06F13/00 ,  G06F13/28 ,  G06F13/30

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Abstract translation: 描述了一种能够访问数据的电路。 该电路包括存储具有第一预定大小的数据块的存储器件; 以及直接存储器访问电路，其耦合到所述存储器件，所述直接存储器电路访问具有大于所述第一预定大小的第二预定尺寸的数据有效载荷; 其中所述直接存储器访问电路响应于具有对应于存储在所述存储器件中的预定数量的数据块的多个地址的描述符来访问所述数据有效载荷。 还公开了一种能够访问数据的方法。