公开(公告)号：US09990131B2

公开(公告)日：2018-06-05

申请号：US14493081

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  James J. Murray ,  Nishit Patel ,  Ahmad R. Ansari

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/30

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/3004 ,  G06F13/1657 ,  G06F2003/0697

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

公开(公告)号：US10824505B1

公开(公告)日：2020-11-03

申请号：US16106691

申请日：2018-08-21

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  Nishit Patel

IPC: G06F11/10 ,  G06F13/40 ,  G06F13/16 ,  G11C29/52

Abstract: An example multi-master system in a system-on-chip (SoC) includes a plurality of master circuits, an error-correcting code (ECC) proxy bridge comprising hardened circuitry in the SoC, a local interconnect configured to couple the plurality of master circuits to the ECC proxy bridge, a memory not having ECC support, and a system interconnect configured to couple the ECC proxy bridge to the memory. The ECC proxy bridge is configured to establish an ECC proxy region in the memory and, for each write transaction from the plurality of master circuits that targets the ECC proxy region, calculate and insert ECC bytes into the respective write transaction.

公开(公告)号：US09558129B2

公开(公告)日：2017-01-31

申请号：US14301008

申请日：2014-06-10

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  James J. Murray ,  Hyun W. Kwon ,  Nishit Patel

IPC: G06F13/00 ,  G06F12/14 ,  G06F13/30 ,  G06F13/28

CPC classification number: G06F12/145 ,  G06F13/00 ,  G06F13/28 ,  G06F13/30

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Abstract translation: 描述了一种能够访问数据的电路。 该电路包括存储具有第一预定大小的数据块的存储器件; 以及直接存储器访问电路，其耦合到所述存储器件，所述直接存储器电路访问具有大于所述第一预定大小的第二预定尺寸的数据有效载荷; 其中所述直接存储器访问电路响应于具有对应于存储在所述存储器件中的预定数量的数据块的多个地址的描述符来访问所述数据有效载荷。 还公开了一种能够访问数据的方法。

公开(公告)号：US10169271B1

公开(公告)日：2019-01-01

申请号：US14526403

申请日：2014-10-28

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Nishit Patel ,  James J. Murray

IPC: G06F13/28 ,  G06F13/36 ,  G06F12/1081

Abstract: Methods and systems are disclosed for transferring data using descriptors to reference memory locations at which data is to be written to or read from. Each descriptor references a respective linked list of descriptor blocks. Each of the descriptor blocks includes a contiguous portion of the memory that stores a plurality of addresses, at which data is to be written to or read from. In response to receiving the data transfer request, a set of data is transferred from a first set of addresses specified in a first descriptor to a second set of addresses specified in a second descriptor by traversing the linked lists of descriptor blocks in the first and second descriptors.

公开(公告)号：US09916129B1

公开(公告)日：2018-03-13

申请号：US14527677

申请日：2014-10-29

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Nishit Patel ,  James J. Murray

IPC: G06F5/14 ,  G06F13/28

CPC classification number: G06F5/14 ,  G06F13/28 ,  G06F2205/126

Abstract: Circuits and methods are disclosed that allow devices to control the flow of DMA transfers to or from the devices using a token based protocol. In one example implementation, a DMA circuit includes a transfer control circuit that performs data transfers over a first data channel of a device, when transactions on the first data channel are enabled. The DMA circuit includes a flow control circuit that increments a token count for a data channel of a device when a token for the data channel is received and decrements the token count for each data transfer on the data channel performed by the DMA circuit. The flow control circuit enables data transfers on the data channel when the token count is greater than 0, and otherwise, disables data transfers on the data channel.

公开(公告)号：US09632869B1

公开(公告)日：2017-04-25

申请号：US14848070

申请日：2015-09-08

Applicant: Xilinx, Inc.

Inventor： Ting Lu ,  Nishit Patel ,  Ahmad R. Ansari ,  James J. Murray ,  Sagheer Ahmad

IPC: G06F12/00 ,  G06F13/16 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1052 ,  G11C29/52 ,  G11C2029/0411

Abstract: In approaches for correction of errors introduced in an interconnect circuit, an ECC proxy circuit is coupled between a first interconnect and the second interconnect, and generates for each of the write transactions from a bus master circuit, a first ECC from and associated with data of the write transaction, and transmits the write transaction and associated first ECC on the second interconnect. The ECC proxy circuit also supplements each of the read transactions from the bus master circuit with a reference to a second ECC associated with data referenced by the read transaction. The ECC proxy circuit transmits the read transaction that references the second ECC on the second interconnect. At least one random access memory (RAM) is coupled to the ECC proxy circuit through the second interconnect. The RAM stores data of each write transaction and the first ECC.

公开(公告)号：US20160085449A1

公开(公告)日：2016-03-24

申请号：US14493081

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  James J. Murray ,  Nishit Patel ,  Ahmad R. Ansari

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/3004 ,  G06F13/1657 ,  G06F2003/0697

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

Abstract translation: 在一个示例中，用于管理第一和第二微处理器之间的存储器的电路，每个微处理器耦合到控制电路，包括：第一和第二存储器电路; 以及耦合到第一和第二存储器电路以及第一和第二微处理器的存储器接口的开关电路，开关电路具有作为输入的模式信号。 开关被配置为基于模式信号选择性地以第一模式或第二模式中的一个模式操作，使得在第一模式中，开关电路将第一存储器电路耦合到第一微处理器和第二存储器的存储器接口 电路连接到第二微处理器的存储器接口，并且在第二模式中，开关电路选择性地将第一或第二存储器电路耦合到第一或第二微处理器的存储器接口。

公开(公告)号：US20150356027A1

公开(公告)日：2015-12-10

申请号：US14301008

申请日：2014-06-10

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  James J. Murray ,  Hyun W. Kwon ,  Nishit Patel

IPC: G06F12/14 ,  G06F13/30

CPC classification number: G06F12/145 ,  G06F13/00 ,  G06F13/28 ,  G06F13/30

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Abstract translation: 描述了一种能够访问数据的电路。 该电路包括存储具有第一预定大小的数据块的存储器件; 以及直接存储器访问电路，其耦合到所述存储器件，所述直接存储器电路访问具有大于所述第一预定大小的第二预定尺寸的数据有效载荷; 其中所述直接存储器访问电路响应于具有对应于存储在所述存储器件中的预定数量的数据块的多个地址的描述符来访问所述数据有效载荷。 还公开了一种能够访问数据的方法。