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    Systems and methods to transport memory mapped traffic amongst integrated circuit devices
    1.
    发明授权
    Systems and methods to transport memory mapped traffic amongst integrated circuit devices 有权

    公开(公告)号：US12019576B2

    公开(公告)日：2024-06-25

    申请号：US17879675

    申请日：2022-08-02

    Applicant: XILINX, INC.

    Inventor： Krishnan Srinivasan ,  Ygal Arbel ,  Sagheer Ahmad ,  Abbas Morshed

    IPC: G06F13/40

    CPC classification number: G06F13/4027 ,  G06F2213/40

    Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

    CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE
    3.
    发明申请
    CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE 审中-公开

    公开(公告)号：US20200026684A1

    公开(公告)日：2020-01-23

    申请号：US16041473

    申请日：2018-07-20

    Applicant: Xilinx, Inc.

    Inventor： Ian A. Swarbrick ,  Sagheer Ahmad ,  Ygal Arbel ,  Dinesh D. Gaitonde

    IPC: G06F15/78 ,  H04L12/24 ,  H04L12/933

    Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

    Inline ECC function for system-on-chip
    4.
    发明授权
    Inline ECC function for system-on-chip 有权

    公开(公告)号：US10346346B1

    公开(公告)日：2019-07-09

    申请号：US15851449

    申请日：2017-12-21

    Applicant: Xilinx, Inc.

    Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

    IPC: G06F15/78 ,  G06F11/10 ,  G06F13/16 ,  G11C29/52

    Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

    MANAGING MEMORY IN A MULTIPROCESSOR SYSTEM
    5.
    发明申请
    MANAGING MEMORY IN A MULTIPROCESSOR SYSTEM 有权
    在多处理器系统中管理存储器

    公开(公告)号：US20160085449A1

    公开(公告)日：2016-03-24

    申请号：US14493081

    申请日：2014-09-22

    Applicant: Xilinx, Inc.

    Inventor： Ygal Arbel ,  Sagheer Ahmad ,  James J. Murray ,  Nishit Patel ,  Ahmad R. Ansari

    IPC: G06F3/06 ,  G06F9/30

    CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/3004 ,  G06F13/1657 ,  G06F2003/0697

    Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

    Abstract translation: 在一个示例中，用于管理第一和第二微处理器之间的存储器的电路，每个微处理器耦合到控制电路，包括：第一和第二存储器电路; 以及耦合到第一和第二存储器电路以及第一和第二微处理器的存储器接口的开关电路，开关电路具有作为输入的模式信号。 开关被配置为基于模式信号选择性地以第一模式或第二模式中的一个模式操作，使得在第一模式中，开关电路将第一存储器电路耦合到第一微处理器和第二存储器的存储器接口 电路连接到第二微处理器的存储器接口，并且在第二模式中，开关电路选择性地将第一或第二存储器电路耦合到第一或第二微处理器的存储器接口。

    CIRCUITS FOR AND METHODS OF ENABLING THE ACCESS TO DATA
    6.
    发明申请
    CIRCUITS FOR AND METHODS OF ENABLING THE ACCESS TO DATA 有权
    电路访问数据的方法和方法

    公开(公告)号：US20150356027A1

    公开(公告)日：2015-12-10

    申请号：US14301008

    申请日：2014-06-10

    Applicant: Xilinx, Inc.

    Inventor： Ygal Arbel ,  James J. Murray ,  Hyun W. Kwon ,  Nishit Patel

    IPC: G06F12/14 ,  G06F13/30

    CPC classification number: G06F12/145 ,  G06F13/00 ,  G06F13/28 ,  G06F13/30

    Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

    Abstract translation: 描述了一种能够访问数据的电路。 该电路包括存储具有第一预定大小的数据块的存储器件; 以及直接存储器访问电路，其耦合到所述存储器件，所述直接存储器电路访问具有大于所述第一预定大小的第二预定尺寸的数据有效载荷; 其中所述直接存储器访问电路响应于具有对应于存储在所述存储器件中的预定数量的数据块的多个地址的描述符来访问所述数据有效载荷。 还公开了一种能够访问数据的方法。

    Circuits for and methods of providing isolation in an integrated circuit
    7.
    发明授权
    Circuits for and methods of providing isolation in an integrated circuit 有权
    在集成电路中提供隔离的电路和方法

    公开(公告)号：US09047474B1

    公开(公告)日：2015-06-02

    申请号：US14187143

    申请日：2014-02-21

    Applicant: Xilinx, Inc.

    Inventor： Sagheer Ahmad ,  Bradley L. Taylor ,  Ygal Arbel

    IPC: H03K19/00 ,  G06F21/60 ,  H03K19/177

    CPC classification number: H03K19/17768 ,  G06F21/575 ,  G06F21/74

    Abstract: A circuit for providing isolation in an integrated circuit is described. The circuit comprises a first circuit block having circuits associated with a first security level; a second circuit block having circuits associated with a second security level; and a third circuit block having programmable resources, the third circuit block providing isolation between the first circuit block and the second circuit block and being programmable to enable connections between the first circuit block and the second circuit block.

    Abstract translation: 描述了用于在集成电路中提供隔离的电路。 该电路包括具有与第一安全级相关联的电路的第一电路块; 具有与第二安全级相关联的电路的第二电路块; 以及具有可编程资源的第三电路块，所述第三电路块提供所述第一电路块和所述第二电路块之间的隔离并且可编程以使得所述第一电路块和所述第二电路块之间能够连接。

    Localized NoC switching interconnect for high bandwidth interfaces
    8.
    发明授权
    Localized NoC switching interconnect for high bandwidth interfaces 有权

    公开(公告)号：US11832035B2

    公开(公告)日：2023-11-28

    申请号：US17232207

    申请日：2021-04-16

    Applicant: XILINX, INC.

    Inventor： Aman Gupta ,  Sagheer Ahmad ,  Ygal Arbel ,  Abbas Morshed ,  Eun Mi Kim

    IPC: H04Q3/00 ,  G06F13/16 ,  G06F13/40

    CPC classification number: H04Q3/0004 ,  G06F13/1668 ,  G06F13/4027

    Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

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