公开(公告)号：US10705993B2

公开(公告)日：2020-07-07

申请号：US16194911

申请日：2018-11-19

Applicant: Xilinx, Inc.

Inventor： Soren T. Soe ,  Idris I. Tarwala ,  Ellery Cochell

IPC: G06F13/28 ,  G06F13/24

Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.

公开(公告)号：US20200159680A1

公开(公告)日：2020-05-21

申请号：US16194911

申请日：2018-11-19

Applicant: Xilinx, Inc.

Inventor： Soren T. Soe ,  Idris I. Tarwala ,  Ellery Cochell

IPC: G06F13/24 ,  G06F13/28

Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.