公开(公告)号：US11720422B1

公开(公告)日：2023-08-08

申请号：US17198887

申请日：2021-03-11

Applicant: Xilinx, Inc.

Inventor： Hem C. Neema ,  Sonal Santan ,  Soren T. Soe ,  Stephen P. Rozum ,  Nik Cimino

IPC: G06F9/54 ,  G06F21/53 ,  G06F8/41 ,  G06F21/57 ,  G06F8/65

CPC classification number: G06F9/545 ,  G06F8/44 ,  G06F21/53 ,  G06F21/572 ,  G06F8/65

Abstract: A unified container file can be selected using computer hardware. The unified container file can include a plurality of files embedded therein used to configure a programmable integrated circuit (IC). The plurality of files can include a first partial configuration bitstream and a second partial configuration bitstream. The unified container file also includes metadata specifying a defined relationship between the first partial configuration bitstream and the second partial configuration bitstream for programming the programmable IC. The defined relationship can be determined using computer hardware by reading the metadata from the unified container file. The programmable IC can be configured, using the computer hardware, based on the defined relationship specified by the metadata using the first partial configuration bitstream and the second partial configuration bitstream.

公开(公告)号：US11086815B1

公开(公告)日：2021-08-10

申请号：US16384624

申请日：2019-04-15

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Soren T. Soe ,  Cheng Zhen

IPC: G06F15/78

Abstract: Supporting multiple clients on a single programmable integrated circuit (IC) can include implementing a first image within the programmable IC in response to a first request for processing to be performed by the programmable IC, wherein the request is from a first process executing in a host data processing system coupled to the programmable IC, receiving, using a processor of the host data processing system, a second request for processing to be performed on the programmable IC from a second and different process executing in the host data processing system while the programmable IC still implements the first image, comparing, using the processor, a second image specified by the second request to the first image, and, in response to determining that the second image matches the first image based on the comparing, granting, using the processor, the second request for processing to be performed by the programmable IC.

公开(公告)号：US20190114533A1

公开(公告)日：2019-04-18

申请号：US15785679

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Jindrich Zejda ,  Elliott Delaye ,  Xiao Teng ,  Sonal Santan ,  Soren T. Soe ,  Ashish Sirasao ,  Ehsan Ghasemi ,  Sean Settle

IPC: G06N3/063 ,  G06N3/10 ,  G06N3/04 ,  G06N3/08

Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator using a library. The neural network application may execute on a host computing system while the neural network accelerator executes on a massively parallel hardware system, e.g., a FPGA. The library operates a pipeline for submitting the tasks received from the neural network application to the neural network accelerator. In one embodiment, the pipeline includes a pre-processing stage, an FPGA execution stage, and a post-processing stage which each correspond to different threads. When receiving a task from the neural network application, the library generates a packet that includes the information required for the different stages in the pipeline to perform the tasks. Because the stages correspond to different threads, the library can process multiple packets in parallel which can increase the utilization of the neural network accelerator on the hardware system.

公开(公告)号：US10956241B1

公开(公告)日：2021-03-23

申请号：US15848691

申请日：2017-12-20

Applicant: Xilinx, Inc.

Inventor： Hem C. Neema ,  Sonal Santan ,  Soren T. Soe ,  Stephen P. Rozum ,  Nik Cimino

IPC: G06F8/41 ,  G06F9/54 ,  G06F21/57 ,  G06F21/53 ,  G06F8/65

Abstract: A computer program product can include a non-transitory computer readable storage medium storing a unified container. The unified container can include a header structure, wherein the header structure has a fixed length and specifies a number of section headers included in the unified container. The unified container can include a plurality of section headers equivalent to the number of section headers specified in the header structure. The unified container can include a plurality of data sections corresponding to the plurality of section headers on a one-to-one basis. The plurality of data sections includes a first data section including a hardware binary and a second data section including a software binary. The hardware binary and the software binary are configured to program a programmable integrated circuit. Each section header specifies a type of data stored in the corresponding data section and specifies a mapping for the corresponding data section.

公开(公告)号：US20240211302A1

公开(公告)日：2024-06-27

申请号：US18145662

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Akila Subramaniam ,  Vinod K. Kathail ,  King Chiu Tam ,  Tung Chuen Kwong ,  Pranjal Joshi ,  Soren T. Soe

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4843 ,  G06F9/5005 ,  G06F9/5061

Abstract: Dynamic provisioning of portions of a data processing array includes receiving, from an executing application, a context request. The context request specifies a requested task to be performed by a data processing array. A configuration for the data processing array is selected from a plurality of configurations for the data processing array. The selected configuration conforms with the context request and is capable of performing the requested task. A determination is made whether the selected configuration is implementable in the data processing array based, at least in part, on a space requirement of the selected configuration and a current status of the data processing array. The selected configuration is selectively implemented in the data processing array based on the determination.

公开(公告)号：US11694066B2

公开(公告)日：2023-07-04

申请号：US15785679

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Jindrich Zejda ,  Elliott Delaye ,  Xiao Teng ,  Sonal Santan ,  Soren T. Soe ,  Ashish Sirasao ,  Ehsan Ghasemi ,  Sean Settle

IPC: G06N3/063 ,  G06N3/10 ,  G06N3/08 ,  G06N3/04 ,  G06V10/94 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06N3/10 ,  G06N3/045 ,  G06V10/955

Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator using a library. The neural network application may execute on a host computing system while the neural network accelerator executes on a massively parallel hardware system, e.g., a FPGA. The library operates a pipeline for submitting the tasks received from the neural network application to the neural network accelerator. In one embodiment, the pipeline includes a pre-processing stage, an FPGA execution stage, and a post-processing stage which each correspond to different threads. When receiving a task from the neural network application, the library generates a packet that includes the information required for the different stages in the pipeline to perform the tasks. Because the stages correspond to different threads, the library can process multiple packets in parallel which can increase the utilization of the neural network accelerator on the hardware system.

公开(公告)号：US10705993B2

公开(公告)日：2020-07-07

申请号：US16194911

申请日：2018-11-19

Applicant: Xilinx, Inc.

Inventor： Soren T. Soe ,  Idris I. Tarwala ,  Ellery Cochell

IPC: G06F13/28 ,  G06F13/24

Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.

公开(公告)号：US20200159680A1

公开(公告)日：2020-05-21

申请号：US16194911

申请日：2018-11-19

Applicant: Xilinx, Inc.

Inventor： Soren T. Soe ,  Idris I. Tarwala ,  Ellery Cochell

IPC: G06F13/24 ,  G06F13/28

Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.

公开(公告)号：US10402223B1

公开(公告)日：2019-09-03

申请号：US15498226

申请日：2017-04-26

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Soren T. Soe

IPC: G06F9/48 ,  G06F13/22 ,  G06F13/28 ,  G06F13/16

Abstract: A heterogeneous computing system can include a host memory and a host processor. The host memory is configured to maintain a write task queue and a read task queue. The host processor is coupled to the host memory and a processing device. The host processor is adapted to store write tasks in the write task queue. The write tasks cause transfer of input data to the processing device. The processing device is adapted to perform offloaded functions. The host processor is adapted to store read tasks in the read task queue. The read tasks cause transfer of results from the offloaded functions from the processing device. The host processor is further adapted to maintain a number of direct memory access (DMA) worker threads corresponding to concurrent data transfer capability of the processing device. Each DMA worker thread is preconfigured to execute tasks from the write task queue or the read task queue.