公开(公告)号：US20240378062A1

公开(公告)日：2024-11-14

申请号：US18316609

申请日：2023-05-12

Applicant: Xilinx, Inc.

Inventor： Nishant Mysore ,  Anurag Dubey ,  Paul Robert Schumacher ,  Jason Richard Villarreal

IPC: G06F9/445 ,  G06F11/34

Abstract: Within an integrated circuit including a processor system and a data processing array, one or more kernels in the processor system are executed in response to a scheduling request from a host data processing system. The one or more kernels receive configuration data for implementing trace or profiling of a user design executable by a plurality of active tiles of the data processing array. Using the one or more kernels, selected tiles of the plurality of active tiles of the data processing array are configured with the configuration data to perform the trace or the profiling. Trace data or profiling data is generated through execution of the user design by the data processing array. The one or more kernels provide the trace data or the profiling data to the host data processing system.

公开(公告)号：US20240378358A1

公开(公告)日：2024-11-14

申请号：US18313945

申请日：2023-05-08

Applicant: Xilinx, Inc.

Inventor： Paul Robert Schumacher ,  Anurag Dubey ,  Jason Richard Villarreal ,  Roger Ng

IPC: G06F30/31

Abstract: Hardware event trace windowing for a data processing array includes executing a user design using a plurality of active tiles of a data processing array disposed in an integrated circuit. A trace start condition is detected subsequent to a start of execution of the user design. In response to the trace start condition, trace data is generated using one or more of the plurality of active tiles of the data processing array. A trace stop condition is detected during execution of the user design. In response to the trace stop condition, the generating the trace data by the one or more of the plurality of active tiles is discontinued.

公开(公告)号：US20240354223A1

公开(公告)日：2024-10-24

申请号：US18305244

申请日：2023-04-21

Applicant: Xilinx, Inc.

Inventor： Paul Robert Schumacher ,  Anurag Dubey ,  Roger Ng ,  Ishita Ghosh ,  Scott H. Jonas ,  Krishnan Subramanian ,  Jason Richard Villarreal

IPC: G06F11/36 ,  G06F11/34

CPC classification number: G06F11/3636 ,  G06F11/348

Abstract: Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.

公开(公告)号：US20240330144A1

公开(公告)日：2024-10-03

申请号：US18193444

申请日：2023-03-30

Applicant: Xilinx, Inc.

Inventor： Ishita Ghosh ,  Elessar Taggart ,  Rishi Bharadwaj Subramanian ,  Jason Richard Villarreal

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3476

Abstract: Offloading trace data from an integrated circuit (IC) can include receiving, by a high-speed debug port (HSDP) trace circuit, streams of trace data from a plurality of compute circuits of different compute circuit types. The compute circuits and the HSDP trace circuit are disposed in a same IC. Compute circuit type identifiers are included within the trace data. The compute circuit type identifiers specify the compute circuit type from which respective ones of the streams of the trace data originate. Debug trace packets (DTPs) are generated from the trace data and transmitted over a high-speed communication link to a trace data storage device (TDSD) external to the IC. Within the TDSD, trace data from the DTPs are stored in a memory of the TDSD.