公开(公告)号：US20240419626A1

公开(公告)日：2024-12-19

申请号：US18336777

申请日：2023-06-16

Applicant: Xilinx, Inc.

Inventor： Paul Robert Schumacher ,  Anurag Dubey

IPC: G06F15/78

Abstract: Performance evaluation of a heterogeneous hardware platform includes implementing a traffic generator design in an integrated circuit. The traffic generator design includes traffic generator kernels including a traffic generator kernel implemented in a data processing array of the integrated circuit and a traffic generator kernel implemented in a programmable logic of the integrated circuit. The traffic generator design is executed in the integrated circuit. The traffic generator kernels implement data access patterns by, at least in part, generating dummy data. Performance data is generated from executing the traffic generator design in the integrated circuit. The performance data is output from the integrated circuit.

公开(公告)号：US20240378358A1

公开(公告)日：2024-11-14

申请号：US18313945

申请日：2023-05-08

Applicant: Xilinx, Inc.

Inventor： Paul Robert Schumacher ,  Anurag Dubey ,  Jason Richard Villarreal ,  Roger Ng

IPC: G06F30/31

Abstract: Hardware event trace windowing for a data processing array includes executing a user design using a plurality of active tiles of a data processing array disposed in an integrated circuit. A trace start condition is detected subsequent to a start of execution of the user design. In response to the trace start condition, trace data is generated using one or more of the plurality of active tiles of the data processing array. A trace stop condition is detected during execution of the user design. In response to the trace stop condition, the generating the trace data by the one or more of the plurality of active tiles is discontinued.

公开(公告)号：US20240354223A1

公开(公告)日：2024-10-24

申请号：US18305244

申请日：2023-04-21

Applicant: Xilinx, Inc.

Inventor： Paul Robert Schumacher ,  Anurag Dubey ,  Roger Ng ,  Ishita Ghosh ,  Scott H. Jonas ,  Krishnan Subramanian ,  Jason Richard Villarreal

IPC: G06F11/36 ,  G06F11/34

CPC classification number: G06F11/3636 ,  G06F11/348

Abstract: Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.

公开(公告)号：US20250004919A1

公开(公告)日：2025-01-02

申请号：US18342615

申请日：2023-06-27

Applicant: Xilinx, Inc.

Inventor： Anurag Dubey ,  Paul Robert Schumacher

IPC: G06F11/36 ,  G06F9/30 ,  G06F13/28

Abstract: An integrated circuit includes a compute circuit and a trace data mover circuit coupled to the compute circuit. The trace data mover circuit is configured to convey trace data generated by the compute circuit to a destination circuit. The trace data mover circuit includes a controller circuit configured to receive a stream of trace data from the compute circuit and generate instructions for writing the trace data. The trace data mover circuit includes a writer circuit configured to write the trace data to the destination circuit responsive to the instructions generated by the controller circuit.

公开(公告)号：US12298887B2

公开(公告)日：2025-05-13

申请号：US18305244

申请日：2023-04-21

Applicant: Xilinx, Inc.

Inventor： Paul Robert Schumacher ,  Anurag Dubey ,  Roger Ng ,  Ishita Ghosh ,  Scott H. Jonas ,  Krishnan Subramanian ,  Jason Richard Villarreal

IPC: G06F11/36 ,  G06F11/34 ,  G06F11/362

Abstract: Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.

公开(公告)号：US20240378062A1

公开(公告)日：2024-11-14

申请号：US18316609

申请日：2023-05-12

Applicant: Xilinx, Inc.

Inventor： Nishant Mysore ,  Anurag Dubey ,  Paul Robert Schumacher ,  Jason Richard Villarreal

IPC: G06F9/445 ,  G06F11/34

Abstract: Within an integrated circuit including a processor system and a data processing array, one or more kernels in the processor system are executed in response to a scheduling request from a host data processing system. The one or more kernels receive configuration data for implementing trace or profiling of a user design executable by a plurality of active tiles of the data processing array. Using the one or more kernels, selected tiles of the plurality of active tiles of the data processing array are configured with the configuration data to perform the trace or the profiling. Trace data or profiling data is generated through execution of the user design by the data processing array. The one or more kernels provide the trace data or the profiling data to the host data processing system.