公开(公告)号：US08635567B1

公开(公告)日：2014-01-21

申请号：US13649593

申请日：2012-10-11

Applicant: Xilinx, Inc.

Inventor： Shay P. Seng ,  Krishnan Subramanian ,  Robert E. Shortt

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5045 ,  G06F2217/02 ,  G06F2217/74

Abstract: A method of circuit design includes receiving a user input selecting a first interface of a circuit block of a circuit design as a source interface in creating a connection within the circuit design and selecting a second interface of the circuit design as a candidate destination interface for the connection using a processor. The method further includes determining compatibility between the second interface and the first interface and indicating compatibility of the second interface with the first interface for the connection.

Abstract translation: 一种电路设计方法包括在电路设计中接收选择电路设计的电路块的第一接口作为源接口的用户输入，并且选择电路设计的第二接口作为候选目标接口 连接使用处理器。 该方法还包括确定第二接口和第一接口之间的兼容性，并指示第二接口与用于连接的第一接口的兼容性。

公开(公告)号：US20240354223A1

公开(公告)日：2024-10-24

申请号：US18305244

申请日：2023-04-21

Applicant: Xilinx, Inc.

Inventor： Paul Robert Schumacher ,  Anurag Dubey ,  Roger Ng ,  Ishita Ghosh ,  Scott H. Jonas ,  Krishnan Subramanian ,  Jason Richard Villarreal

IPC: G06F11/36 ,  G06F11/34

CPC classification number: G06F11/3636 ,  G06F11/348

Abstract: Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.