公开(公告)号：US08842034B1

公开(公告)日：2014-09-23

申请号：US13760468

申请日：2013-02-06

Applicant: Xilinx, Inc.

Inventor： Jingfeng Gong

IPC: H03M1/78 ,  H01L23/522

CPC classification number: H01C1/16 ,  H03M1/68 ,  H03M1/765

Abstract: A resistor network implemented in an integrated circuit includes a first plurality of interconnect traces coupled in series at a first plurality of nodes; a first plurality of switches coupled between the first plurality of nodes and an output node; a second plurality of interconnect traces coupled in series at a second plurality of nodes; and a second plurality of switches coupled between the second plurality of nodes and the output node, wherein a voltage at the output node is generated in response to a resistance of the resistor network based upon a configuration of the first plurality of switches and the second plurality of switches.

Abstract translation: 在集成电路中实现的电阻网络包括在第一多个节点处串联耦合的第一多个互连迹线; 耦合在所述第一多个节点和输出节点之间的第一多个开关; 在第二多个节点处串联耦合的第二多个互连迹线; 以及耦合在第二多个节点和输出节点之间的第二多个开关，其中响应于基于第一多个开关和第二多个开关的配置的电阻器网络的电阻而产生输出节点处的电压 的开关。

公开(公告)号：US09432007B1

公开(公告)日：2016-08-30

申请号：US14461223

申请日：2014-08-15

Applicant: Xilinx, Inc.

Inventor： Jingfeng Gong ,  Cheng-Hsiang Hsieh

IPC: H03K5/22 ,  H03K5/1252 ,  H03K5/24 ,  H03K3/012

CPC classification number: H03K5/1252 ,  H03K5/2481

Abstract: An out-of-band (OOB) detection circuit includes: a positive input node; a negative input node; a resistive circuit comprising a first resistor coupled between a first supply node and a first node, a variable resistor coupled between the first node and a second node, and a second resistor coupled between the second node and a ground; a first comparator configured to compare a difference between a positive input signal received at the positive input node and a negative input signal received at the negative input node against a positive threshold value, and a second comparator configured to compare the difference between the positive input signal received at the positive input node and the negative input signal received at the negative input node against a negative threshold value.

Abstract translation: 带外（OOB）检测电路包括：正输入节点; 负输入节点; 电阻电路，包括耦合在第一电源节点和第一节点之间的第一电阻器，耦合在第一节点和第二节点之间的可变电阻器以及耦合在第二节点和地之间的第二电阻器; 第一比较器，被配置为比较在正输入节点处接收的正输入信号与在负输入节点处接收的负输入信号之间的差相对于正阈值的差;以及第二比较器，被配置为将正输入信号 在负输入节点接收的负输入信号和负输入节点接收的负输入信号抵消负阈值。