公开(公告)号：US20150180642A1

公开(公告)日：2015-06-25

申请号：US14135071

申请日：2013-12-19

Applicant: Xilinx, Inc.

Inventor： Cheng-Hsiang Hsieh ,  Kun-Yung Chang ,  Jafar Savoj

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

CPC classification number: H04L7/0025 ,  H04L7/0062 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/03057 ,  H04L25/03885

Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

Abstract translation: 描述了在集成电路中实现的数据接收器。 数据接收机包括接收数据信号的输入端; 耦合以接收所述数据信号的第一均衡电路，其中所述第一均衡电路用于接收所述数据信号的数据; 以及耦合以接收所述数据信号的第二均衡电路，其中所述第二均衡电路用于调整时钟相位偏移。

公开(公告)号：US09432007B1

公开(公告)日：2016-08-30

申请号：US14461223

申请日：2014-08-15

Applicant: Xilinx, Inc.

Inventor： Jingfeng Gong ,  Cheng-Hsiang Hsieh

IPC: H03K5/22 ,  H03K5/1252 ,  H03K5/24 ,  H03K3/012

CPC classification number: H03K5/1252 ,  H03K5/2481

Abstract: An out-of-band (OOB) detection circuit includes: a positive input node; a negative input node; a resistive circuit comprising a first resistor coupled between a first supply node and a first node, a variable resistor coupled between the first node and a second node, and a second resistor coupled between the second node and a ground; a first comparator configured to compare a difference between a positive input signal received at the positive input node and a negative input signal received at the negative input node against a positive threshold value, and a second comparator configured to compare the difference between the positive input signal received at the positive input node and the negative input signal received at the negative input node against a negative threshold value.

Abstract translation: 带外（OOB）检测电路包括：正输入节点; 负输入节点; 电阻电路，包括耦合在第一电源节点和第一节点之间的第一电阻器，耦合在第一节点和第二节点之间的可变电阻器以及耦合在第二节点和地之间的第二电阻器; 第一比较器，被配置为比较在正输入节点处接收的正输入信号与在负输入节点处接收的负输入信号之间的差相对于正阈值的差;以及第二比较器，被配置为将正输入信号 在负输入节点接收的负输入信号和负输入节点接收的负输入信号抵消负阈值。

公开(公告)号：US09356775B1

公开(公告)日：2016-05-31

申请号：US14795169

申请日：2015-07-09

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Cheng-Hsiang Hsieh ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/033 ,  H04L7/04

CPC classification number: H04L7/041 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337

Abstract: Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code or a crossing PI code in a clock and data recovery (CDR) circuit until one or more preset criteria are satisfied. One example method generally includes determining that a condition has been met; based on the determination, stepping, in a CDR circuit, at least one of a data PI code or a crossing PI code for each cycle of a clock; stopping the stepping based on one or more criteria to generate a predetermined state of the data PI code and the crossing PI code, wherein the predetermined state comprises an offset between the data PI code and the crossing PI code; receiving a data stream; and performing clock and data recovery on the data stream based on the offset between the data PI code and the crossing PI code.

Abstract translation: 描述了用于在时钟和数据恢复（CDR）电路中同步地步进数据相位内插器（PI）代码或交叉PI代码中的至少一个的方法和装置，直到满足一个或多个预设标准。 一个示例性方法通常包括确定已经满足条件; 基于所述确定，在CDR电路中步进每个时钟周期的数据PI代码或交叉PI代码中的至少一个; 基于一个或多个标准停止步进以产生数据PI代码和交叉PI代码的预定状态，其中预定状态包括数据PI代码和交叉PI代码之间的偏移量; 接收数据流; 并且基于数据PI代码和交叉PI代码之间的偏移在数据流上执行时钟和数据恢复。

公开(公告)号：US09065601B1

公开(公告)日：2015-06-23

申请号：US13842604

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Michael O. Jenkins ,  Cheng-Hsiang Hsieh ,  Christopher J. Borrelli

IPC: H04L7/04 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0337 ,  H03L7/0812 ,  H03L7/093 ,  H04L7/0025 ,  H04L7/033

Abstract: A receiver in an integrated circuit device is described. The circuit comprises a receiver having a clock and data recovery circuit coupled to receive data signals modulated with a transmitter clock signal; and a clock generator coupled to receive an output of the clock and data recovery circuit, the clock generator providing a modulated reference clock to the receiver, based upon a reference clock signal which is independent of the transmitter clock signal; wherein the modulated reference clock provided to the receiver is synchronized with the transmitter clock signal. A method of receiving data in an integrated circuit is also described.

Abstract translation: 描述了集成电路器件中的接收器。 该电路包括具有时钟和数据恢复电路的接收器，该时钟和数据恢复电路被耦合以接收用发射机时钟信号调制的数据信号; 以及时钟发生器，其耦合以接收所述时钟和数据恢复电路的输出，所述时钟发生器基于独立于所述发射机时钟信号的参考时钟信号向所述接收机提供调制参考时钟; 其中提供给接收机的调制参考时钟与发射机时钟信号同步。 还描述了在集成电路中接收数据的方法。

公开(公告)号：US09325489B2

公开(公告)日：2016-04-26

申请号：US14135071

申请日：2013-12-19

Applicant: Xilinx, Inc.

Inventor： Cheng-Hsiang Hsieh ,  Kun-Yung Chang ,  Jafar Savoj

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

CPC classification number: H04L7/0025 ,  H04L7/0062 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/03057 ,  H04L25/03885

Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

Abstract translation: 描述了在集成电路中实现的数据接收器。 数据接收机包括接收数据信号的输入端; 耦合以接收所述数据信号的第一均衡电路，其中所述第一均衡电路用于接收所述数据信号的数据; 以及耦合以接收所述数据信号的第二均衡电路，其中所述第二均衡电路用于调整时钟相位偏移。

公开(公告)号：US08923463B1

公开(公告)日：2014-12-30

申请号：US14013283

申请日：2013-08-29

Applicant: Xilinx, Inc.

Inventor： Michael O. Jenkins ,  Cheng-Hsiang Hsieh

IPC: H04L7/02 ,  H04L25/02

CPC classification number: H04L7/0334 ,  H04L25/069

Abstract: In an apparatus, a receiver includes a clock data recovery module to provide a dense distribution of waveform edges across an adjustment range, and an eye scan circuit to obtain samples at a first sample position and a second sample position to provide an error count for a sample count for the samples. An eye scan module, coupled to the receiver, is configured to: scan for the samples at the first sample position of a first type for each of a plurality of sample positions of a second type to obtain an error count for a sample count for each of the plurality of sample positions; locate a threshold BER from the scan; determine an amount and a direction of a sample offset at the threshold BER from a reference location; and adjust either the first sample position or the second sample position responsive to the amount and the direction.

Abstract translation: 在一种装置中，接收机包括时钟数据恢复模块，用于在调整范围内提供波形边缘的密集分布，以及眼睛扫描电路，以获得在第一采样位置和第二采样位置处的采样，以提供误差计数 样品的样品数量。 耦合到接收器的眼睛扫描模块被配置为：针对第二类型的多个样本位置中的每一个扫描第一类型的第一样本位置处的样本，以获得每个样本计数的错误计数 的多个样本位置; 从扫描中定位阈值BER; 从参考位置确定在阈值BER处的样本偏移的量和方向; 并且响应于量和方向来调整第一样品位置或第二样品位置。