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公开(公告)号：US20240259033A1
公开(公告)日：2024-08-01
申请号：US18415655
申请日：2024-01-18
发明人： Hiroshi TSUCHI
CPC分类号： H03M1/765 , G09G3/3688 , G09G2320/0626
摘要： The disclosure includes: a differential amplifier, and a first decoder assigning and supplying a first or second voltage to each of a plurality of input terminals based on (K+1) bits of digital data. The differential amplifier includes 2K differential pairs each driven by a tail current received individually, and a tail current control circuit supplying first to 2Kth tail currents to the 2K differential pairs and controlling first to 2Kth current ratios for the first to 2Kth tail currents based on the digital data. The tail current control circuit has a basic configuration that sets each of the first to 2Kth current ratios to a maximum value, a minimum value, or an intermediate value among three predetermined values, and increases one of the maximum and minimum values and decreases the other for the current ratio of the tail currents supplied to two predetermined differential pairs.
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公开(公告)号：US11683046B2
公开(公告)日：2023-06-20
申请号：US17878807
申请日：2022-08-01
发明人： Jingguang Wang , Jing Wang , Robert Roze , Kambiz Vakilian
CPC分类号： H03M1/005 , H03M1/0881 , H03M1/682 , H03M1/747 , H03M1/765
摘要： The systems and methods discussed herein utilized a wireless or wired transceiver having a transmitter and a receiver. The transceiver is configured to reduce distortion contributions associated with echo cancelling. The transmitter provides a replica signal and a transmit signal. The replica signal and the transmit signal can be provided using a common switch.
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公开(公告)号：US11670216B2
公开(公告)日：2023-06-06
申请号：US17379970
申请日：2021-07-19
发明人： Hiroshi Tsuchi
CPC分类号： G09G3/2092 , H03M1/682 , H03M1/765 , G09G2310/027
摘要： A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to xth input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to xth input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to xth input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.
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公开(公告)号：US10340935B1
公开(公告)日：2019-07-02
申请号：US15869617
申请日：2018-01-12
发明人： Hirohisa Tanabe , Seiichi Ozawa
CPC分类号： H03M1/1071 , H03M1/765
摘要： A thermometer-coded Digital to Analog Converter (DAC) is described, whose output is changed with fast speed, and reduced output overshoot or undershoot. The thermometer-coded DAC has selection switches and an up/down counter, with DAC codes separated into higher and lower bits. The lower bits increase up to a maximum code, then decrease. The configuration of resistors in the DAC reduces output spike, especially at the DAC code changing point.
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公开(公告)号：US20180337647A1
公开(公告)日：2018-11-22
申请号：US15982548
申请日：2018-05-17
CPC分类号： H03F3/45192 , H03F2200/18 , H03M1/124 , H03M1/66 , H03M1/68 , H03M1/742 , H03M1/765
摘要： A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.
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公开(公告)号：US20180152656A1
公开(公告)日：2018-05-31
申请号：US15797085
申请日：2017-10-30
发明人： Osamu MATSUMOTO , Fukashi MORISHITA
摘要： Provided is a solid-state imaging device capable of increasing the speed of an A/D converter. The solid-state imaging device includes a successive approximation A/D converter that performs A/D conversion on an analog pixel signal. The successive approximation A/D converter includes a D/A converter, a comparator, and a successive approximation register. The D/A converter converts a digital reference signal to an analog reference signal. The successive approximation register operates based on the result of comparison by the comparator to generate the digital reference signal in such a manner that the analog reference signal approximates the analog pixel signal. The D/A converter includes a split capacitor, first capacitors, second capacitors, a switch array, a third capacitor, and a multiplexer. The first capacitors each have a first electrode coupled to the output node. The second capacitors are coupled to a second electrode of the split capacitor. The switch array is coupled to a second electrode of each of the first and second capacitors and is adapted to generate the analog reference signal at the output node by selectively applying a first reference voltage. The third capacitor is coupled to the second electrode of the split capacitor. The multiplexer is coupled to a second electrode of the third capacitor and is adapted to generate the analog reference signal at the output node by selectively applying a second reference voltage.
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公开(公告)号：US20180083648A1
公开(公告)日：2018-03-22
申请号：US15697233
申请日：2017-09-06
申请人： Apple Inc.
发明人： Baris Cagdaser , Derek K. Shaeffer , Hopil Bae , Jesse Aaron Richmond , Jie Won Ryu , Kingsuk Brahma , Mohammad B. Vahid Far , Shingo Hatanaka , Yafei Bi , Yuichi Okuda
CPC分类号： H03M1/785 , G09G2320/0276 , H03M1/682 , H03M1/747 , H03M1/765
摘要： A device includes a resistor string that includes a plurality resistors with voltage taps disposed therebetween. The device may select one particular voltage tap of the plurality of voltage taps based on received gray level data for a pixel of a display. The device also includes a first amplifier that may be coupled to a first terminal end of the resistor string. The device additionally includes a second amplifier that may be coupled to a second terminal end of the resistor string, wherein the plurality of voltage taps may each supply a tap voltage derived from a voltage between the first amplifier and the second amplifier, wherein any tap amplifier of the device coupled to a voltage tap of the plurality of voltage taps provides a reference voltage thereto.
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公开(公告)号：US20180006660A1
公开(公告)日：2018-01-04
申请号：US15703324
申请日：2017-09-13
申请人： INNOAXIS CO., LTD
发明人： Hwi-Cheol KIM
IPC分类号： H03M1/78 , G11C19/00 , G09G3/20 , H03M7/00 , H03K19/0185
CPC分类号： H03M1/785 , G09G3/2092 , G09G2300/0408 , G09G2300/0828 , G09G2300/0871 , G09G2310/027 , G09G2310/0289 , G09G2310/0291 , G11C19/00 , H03K19/018521 , H03M1/765 , H03M7/00
摘要： A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.
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公开(公告)号：US09791482B1
公开(公告)日：2017-10-17
申请号：US15607683
申请日：2017-05-30
申请人： Active-Semi, Inc.
CPC分类号： H02M1/32 , G01R19/2513 , G01R31/362 , G05B11/28 , G05B15/02 , G05F1/66 , H01H85/0241 , H02H3/08 , H02J9/061 , H02M1/08 , H02M3/156 , H02M3/158 , H02M3/1582 , H02M3/1588 , H02M2001/0009 , H03M1/122 , H03M1/765
摘要： A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.
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公开(公告)号：US09705402B1
公开(公告)日：2017-07-11
申请号：US15201265
申请日：2016-07-01
申请人： Active-Semi, Inc.
CPC分类号： H02M1/32 , G01R19/2513 , G01R31/362 , G05B11/28 , G05B15/02 , G05F1/66 , H01H85/0241 , H02H3/08 , H02J9/061 , H02M1/08 , H02M3/156 , H02M3/158 , H02M3/1582 , H02M3/1588 , H02M2001/0009 , H03M1/122 , H03M1/765
摘要： A power loss protection integrated circuit includes a current switch circuit (eFuse), a VIN terminal, a VOUT terminal, a buck/boost controller, and a storage capacitor terminal STR. The controller is adapted to work: 1) as a boost to take a low voltage from the VOUT terminal and to output a larger charging voltage onto the STR terminal, or 2) as a buck to take a higher voltage from the STR terminal and to buck it down to a lower voltage required on the VOUT terminal. The current switch circuit outputs a digital undervoltage signal (UV) and a digital high current signal (HC). These signals are communicated on-chip to the controller. Asserting UV causes the converter to begin operating in the buck mode. Asserting HC prevents the converter from operating in the boost mode.
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