公开(公告)号：US09824172B1

公开(公告)日：2017-11-21

申请号：US15078400

申请日：2016-03-23

Applicant: Xilinx, Inc.

Inventor： Kecheng Hao ,  Hongbin Zheng ,  Stephen A. Neuendorffer

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Implementing circuitry from an application can include determining a data flow of an application including a producer function, a loop construct, and a consumer function and creating a new function including contents of a body of the loop construct. A circuit design can be generated from the application including a producer function circuit block, a new function circuit block, and a consumer function circuit block. Control circuitry for each circuit block can be included within the circuit design. The control circuitry of the new function circuit block can initiate operation of the new function circuit block according to a loop induction variable of the loop construct.

公开(公告)号：US09710584B1

公开(公告)日：2017-07-18

申请号：US15078347

申请日：2016-03-23

Applicant: Xilinx, Inc.

Inventor： Kecheng Hao ,  Hongbin Zheng ,  Stephen A. Neuendorffer

IPC: G06F17/50 ,  G06F3/06

CPC classification number: G06F17/505 ,  G06F8/443

Abstract: Implementing circuitry from an application may include partitioning an array of the application into a plurality of virtual blocks according to a streaming dimension of the array and determining that a first function and a second function of the application that access the array have same access patterns for the virtual blocks of the array. A first-in-first out (FIFO) memory may be included in a circuit design implementing the application. The FIFO memory couples a first circuit block implementing the first function with a second circuit block implementing the second function. Control circuitry is included within the circuit design. The control circuitry may be configured to implement concurrent operation of the first circuit block and the second circuit block by controlling accesses of the first circuit block and the second circuit block to a plurality of buffers in the FIFO memory.

公开(公告)号：US11373024B1

公开(公告)日：2022-06-28

申请号：US16353981

申请日：2019-03-14

Applicant: Xilinx, Inc.

Inventor： Sahil Goyal ,  Hongbin Zheng ,  Mahesh Attarde ,  Amit Kasat

IPC: G06F30/33 ,  G06F30/331

Abstract: The disclosed approaches involve executing simulator-parallel processes that correspond to states of a finite state machine representation of a circuit design. Execution of each simulator-parallel process is initiated in response to an event generated by another one of the simulator-parallel processes. A data access transaction of the circuit design is simulated by calling a first function of a wrapper from a first process of the simulator-parallel processes. The first process waits for an estimated number of simulation clock cycles. The estimated number of simulation clock cycles represents an actual time period required to complete an actual data access transaction.