公开(公告)号：US10169177B1

公开(公告)日：2019-01-01

申请号：US15802274

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Banadappa V Shivaray ,  Pranjal Chauhan ,  Pramod Surathkal ,  Alex S. Warshofsky ,  Tomai Knopp ,  Soumitra Kumar Bhowmick ,  Ahmad R. Ansari

IPC: G06F11/22 ,  G06F17/50 ,  H03K19/003

Abstract: Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.

公开(公告)号：US10234505B1

公开(公告)日：2019-03-19

申请号：US15443990

申请日：2017-02-27

Applicant: Xilinx, Inc.

Inventor： Banadappa V. Shivaray ,  Ismed D. Hartanto ,  Alex S. Warshofsky ,  Pranjal Chauhan

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

Abstract: A disclosed integrated circuit includes first and second clock generation circuits, a stagger circuit, and a plurality of scan chains. The first clock generation circuit receives a first clock signal and generates a first set of clock pulses having a first frequency in response to receipt of a first clock trigger signal and a first enable signal. The second clock generation circuit receives a second clock signal and generates a second set of clock pulses having a second frequency in response to receipt of a second clock trigger signal and a second enable signal. The stagger circuit generates the first and second clock trigger signals from the global trigger signal at different times. The first set of clock pulses are staggered relative to the second set of clock pulses. The plurality of scan chains test functionality of logic circuitry within the IC chip using the first and second set of clock pulses.