公开(公告)号：US10234505B1

公开(公告)日：2019-03-19

申请号：US15443990

申请日：2017-02-27

Applicant: Xilinx, Inc.

Inventor： Banadappa V. Shivaray ,  Ismed D. Hartanto ,  Alex S. Warshofsky ,  Pranjal Chauhan

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

Abstract: A disclosed integrated circuit includes first and second clock generation circuits, a stagger circuit, and a plurality of scan chains. The first clock generation circuit receives a first clock signal and generates a first set of clock pulses having a first frequency in response to receipt of a first clock trigger signal and a first enable signal. The second clock generation circuit receives a second clock signal and generates a second set of clock pulses having a second frequency in response to receipt of a second clock trigger signal and a second enable signal. The stagger circuit generates the first and second clock trigger signals from the global trigger signal at different times. The first set of clock pulses are staggered relative to the second set of clock pulses. The plurality of scan chains test functionality of logic circuitry within the IC chip using the first and second set of clock pulses.

公开(公告)号：US10169177B1

公开(公告)日：2019-01-01

申请号：US15802274

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Banadappa V Shivaray ,  Pranjal Chauhan ,  Pramod Surathkal ,  Alex S. Warshofsky ,  Tomai Knopp ,  Soumitra Kumar Bhowmick ,  Ahmad R. Ansari

IPC: G06F11/22 ,  G06F17/50 ,  H03K19/003

Abstract: Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.

公开(公告)号：US08937496B1

公开(公告)日：2015-01-20

申请号：US14464661

申请日：2014-08-20

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Alex S. Warshofsky ,  Ygal Arbel

IPC: G01R23/02 ,  H03D3/00 ,  H03K9/06 ,  H03K5/19

CPC classification number: H03K5/19

Abstract: A clock monitoring circuit is disclosed. The clock monitoring circuit is configured to receive first and second clock signals generated in respective clock domains. The clock monitoring circuit includes a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal. The first counter outputs a count value indicating the number of counted clock cycles. The clock monitoring circuit also includes a threshold comparator circuit configured to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of an expected range.

Abstract translation: 公开了一种时钟监控电路。 时钟监视电路被配置为接收在各个时钟域中产生的第一和第二时钟信号。 时钟监视电路包括第一计数器，其被配置为对由第二时钟信号的时钟周期描绘的第一时间段对第一时钟信号的时钟周期进行计数。 第一计数器输出指示计数时钟周期数的计数值。 时钟监视电路还包括阈值比较器电路，该阈值比较器电路被配置为响应于第一时间段的期满和由第一计数器输出的第一计数值落在期望范围之外而产生误差信号。