公开(公告)号：US09411688B1

公开(公告)日：2016-08-09

申请号：US14103723

申请日：2013-12-11

Applicant: Xilinx, Inc.

Inventor： Ramakrishna G. Poolla ,  Yatharth K. Kochar ,  Krishna C. Patakamuri

IPC: G06F11/14 ,  H03K19/177

CPC classification number: G06F11/1417 ,  H03K19/17764

Abstract: In some disclosed implementations, a system-on-chip on a first IC die includes a boot loader circuit configured to search a first boot device, of a plurality of boot devices coupled to and external to the first IC die, for an uncorrupt boot image. The boot loader circuit is configured to search a second boot device of the plurality of boot devices for an uncorrupt boot image, in response to failing to find an uncorrupt boot image in the first boot device. The boot loader is also configured to load a set of instructions included in the uncorrupt boot image into a memory circuit of the SOC, in response to finding an uncorrupt boot image.

Abstract translation: 在一些公开的实现中，第一IC芯片上的片上系统包括引导加载器电路，其被配置为搜索耦合到第一IC管芯并且在第一IC管芯外部的多个引导器件中的第一引导器件用于未破坏的引导映像 。 引导加载器电路被配置为响应于在第一引导设备中找不到未破坏的引导映像而搜索多个引导设备中的第二引导设备的未破坏的引导映像。 引导加载程序还被配置为响应于发现未破坏的引导映像而将包含在未破坏的引导映像中的一组指令加载到SOC的存储器电路中。

公开(公告)号：US11280829B1

公开(公告)日：2022-03-22

申请号：US16721843

申请日：2019-12-19

Applicant: Xilinx, Inc.

Inventor： Ramakrishna G. Poolla ,  Krishna C. Patakamuri ,  James D. Wesselkamper ,  Jason J. Moore ,  Edward S. Peterson ,  Steven E. McNeil

IPC: H04L29/06 ,  G01R31/317 ,  G01R31/3177 ,  G06F21/44 ,  H04L9/32 ,  G06F21/76 ,  H04L9/30

Abstract: Disclosed approaches for controlling debug access to an integrated circuit (IC) device include receiving a debug packet by a debug interface circuit of the IC device. The debug interface circuit authenticates the debug packet in response to the debug packet having a command code that specifies enable debug mode or a command code that specifies disable debug mode. In response to the debug packet passing authentication and the command code specifying enable, the debug interface circuit enables debug mode of the IC device. In response to the debug packet passing authentication and the command code specifying disable, the debug interface circuit disables the debug mode of the IC device. In response to the debug packet failing authentication, the debug interface circuit rejects the debug packet.

公开(公告)号：US10657265B1

公开(公告)日：2020-05-19

申请号：US15848304

申请日：2017-12-20

Applicant: Xilinx, Inc.

Inventor： Ramakrishna G. Poolla ,  Krishna C. Patakamuri

IPC: G06F21/00 ,  G06F21/57 ,  G06F21/74 ,  G06F21/60 ,  G06F3/06

Abstract: Method and system generally relating to integrated circuits are disclosed. In such a method, a secure lockdown mode for the integrated circuit is initiated. System states of a system internal to the integrated circuit are obtained after initiation of the secure lockdown mode. This obtaining of the system states includes: reading out of the system states from storage devices internal to the integrated circuit; and loading the system states into temporary storage of the integrated circuit. The system states are output via a port of the integrated circuit before closing the port responsive to the secure lockdown mode.

公开(公告)号：US09652252B1

公开(公告)日：2017-05-16

申请号：US14527709

申请日：2014-10-29

Applicant: Xilinx, Inc.

Inventor： Yatharth K. Kochar ,  Ramakrishna G. Poolla ,  Krishna C. Patakamuri ,  Madhubala Sharma

IPC: G06F12/02 ,  G06F9/44 ,  G06F1/32

CPC classification number: G06F9/4408 ,  G06F1/3212 ,  G06F1/3234 ,  G06F9/441 ,  G06F12/0238 ,  Y02D10/174

Abstract: Circuits and methods for power dependent selection of boot images are disclosed. In an example implementation, an apparatus includes a memory circuit and a processor disposed on an integrated circuit die. The processor is configured to retrieve and execute instructions from the memory circuit. The apparatus also includes a power management circuit configured to determine a value indicative of an amount of power available to power the IC die. A boot loader circuit is coupled to the power management circuit and is configured to select one of a plurality of boot images based on the determined value indicative of the amount of power available. The boot loader circuit loads a set of instructions included in the selected one of the boot images into the memory circuit and enables the processor to execute the set of instructions.