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公开(公告)号：US10978167B1
公开(公告)日：2021-04-13
申请号：US16806546
申请日：2020-03-02
Applicant: Xilinx, Inc.
Inventor： James D. Wesselkamper , Edward S. Peterson , Jason J. Moore , Steven E. McNeil
Abstract: A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The efuse security reads the data from the storage circuit and generates an alert signal having a state that indicates a security violation in response to data representative of the value of the signal from the first sense amplifier indicating a logic-0 value or data representative of the value of the signal from the second sense amplifier indicating a logic-1 value.
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公开(公告)号：US09165143B1
公开(公告)日：2015-10-20
申请号：US13833177
申请日：2013-03-15
Applicant: Xilinx, Inc.
Inventor： Lester S. Sanders , Yatharth K. Kochar , Steven E. McNeil , Jason J. Moore , Roger D. Flateau, Jr. , Lawrence C. Hung
CPC classification number: G06F21/575 , G06F21/572 , G06F21/76
Abstract: A method relating generally to loading a boot image is disclosed. In such a method, a header of a boot image file is read by boot code executed by a system-on-chip. It is determined whether the header read has an authentication certificate. If the header has the authentication certificate, authenticity of the header is verified with the first authentication certificate. It is determined whether the header is encrypted. If the header is encrypted, the header is decrypted.
Abstract translation: 公开了一般涉及加载引导图像的方法。 在这种方法中，通过由片上系统执行的引导代码来读取引导映像文件的标题。 确定头读取是否具有认证证书。 如果标头具有认证证书，则使用第一认证证书验证报头的真实性。 确定头部是否被加密。 如果标题被加密，则头部被解密。
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公开(公告)号：US11379580B1
公开(公告)日：2022-07-05
申请号：US16819864
申请日：2020-03-16
Applicant: Xilinx, Inc.
Inventor： James D. Wesselkamper , Edward S. Peterson , Jason J. Moore , Steven E. McNeil , Roger D. Flateau, Jr. , Danny Tsung-Heng Wu , Boon Y. Ang
Abstract: An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.
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公开(公告)号：US11582021B1
公开(公告)日：2023-02-14
申请号：US16690097
申请日：2019-11-20
Applicant: Xilinx, Inc.
Inventor： James D. Wesselkamper , Nathan A. Menhorn , Jason J. Moore
Abstract: Disclosed approaches for validating initialization vectors determining by a configuration control circuit whether or not an input initialization vector is within a range of valid initialization vectors. In response to determining that the initialization vector is within the range of valid initialization vectors, the configuration control circuit decrypts the ciphertext into plaintext using the input initialization vector and configures a memory circuit with the plaintext. In response to determining that the first initialization vector is outside the range of valid initialization vectors, the configuration control circuit signals that the first initialization vector is invalid.
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公开(公告)号：US10288496B1
公开(公告)日：2019-05-14
申请号：US15236703
申请日：2016-08-15
Applicant: Xilinx, Inc.
Inventor： James D. Wesselkamper , Frank C. Wirtz, II , Giulio Corradi , Jason J. Moore
Abstract: Methods and circuits are disclosed for measuring temperature and/or voltage using ring oscillators. In an example implementation, temperature and/or voltage are determined using an iterative measurements of a ring oscillator. The ring oscillator oscillates with a different voltage-temperature response in each of the first, second and third modes. In each iteration, a first set of indications of frequency are determined for a ring oscillator in a first mode, a second mode, and a third mode. A coarse temperature estimate and a coarse voltage estimate of the ring oscillator are determined based on the indications of frequency measured in a first iteration. A more accurate temperature estimate and a more accurate voltage estimate of the ring oscillator are determined as a function of a second set of indications of frequency measured in a second iteration, the coarse temperature estimate, and the coarse voltage estimate.
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Patent Agency Ranking
公开(公告)号：US09530022B1
公开(公告)日：2016-12-27
申请号：US14502996
申请日：2014-09-30
Applicant: Xilinx, Inc.
Inventor： Jason J. Moore , James B. Anderson , James D. Wesselkamper , Stephen M. Trimberger
Abstract: In one approach for protecting a design, a plurality of implementations of the design are generated. Each implementation includes an identification function. One of the implementations is selected as a current implementation, and the current implementation is installed on one or more electronic systems. For each electronic system, a method determines whether or not the current implementation is an authorized version on the electronic system from an output value of the identification function. If in the current implementation is not an authorized version on the electronic system, a signal is output indicating that the current implementation is not an authorized version on the electronic system. Periodically, another one of the implementations is selected as a new current implementation, and the new current installation is used for installations on one or more electronic systems.
Abstract translation: 在保护设计的一种方法中，生成设计的多个实现。 每个实现包括识别功能。 选择其中一个实现作为当前实现，并且当前实现被安装在一个或多个电子系统上。 对于每个电子系统，一种方法从识别功能的输出值确定当前实现是否是电子系统上的授权版本。 如果在当前实现中不是电子系统上的授权版本，则输出指示当前实现不是电子系统上的授权版本的信号。 周期性地，另外一个实现被选择为新的当前实现，并且新的当前安装被用于一个或多个电子系统上的安装。
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公开(公告)号：US09218505B1
公开(公告)日：2015-12-22
申请号：US13756151
申请日：2013-01-31
Applicant: Xilinx, Inc.
Inventor： James D. Wesselkamper , James B. Anderson , Jason J. Moore , Edward S. Peterson
CPC classification number: G06F21/72 , G06F21/755 , H04L9/003 , H04L9/3239
Abstract: Approaches for configuring a programmable integrated circuit (IC) are disclosed. Encrypted configuration data is input to the programmable IC, and the encrypted configuration data is stored in configuration memory of the programmable IC. As the encrypted configuration data is input, a determination is made as to whether or not the encrypted configuration data is authentic. In response to the encrypted configuration data being authentic, the encrypted configuration data is read from the configuration memory and decrypted, and the decrypted configuration data is stored back in the configuration memory.
Abstract translation: 公开了用于配置可编程集成电路（IC）的方法。 加密的配置数据被输入到可编程IC，并且加密的配置数据被存储在可编程IC的配置存储器中。 当输入加密配置数据时，确定加密配置数据是否可信。 响应于加密的配置数据是可信的，从配置存储器中读取加密的配置数据并进行解密，并将解密的配置数据存储在配置存储器中。
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公开(公告)号：US11280829B1
公开(公告)日：2022-03-22
申请号：US16721843
申请日：2019-12-19
Applicant: Xilinx, Inc.
Inventor： Ramakrishna G. Poolla , Krishna C. Patakamuri , James D. Wesselkamper , Jason J. Moore , Edward S. Peterson , Steven E. McNeil
IPC: H04L29/06 , G01R31/317 , G01R31/3177 , G06F21/44 , H04L9/32 , G06F21/76 , H04L9/30
Abstract: Disclosed approaches for controlling debug access to an integrated circuit (IC) device include receiving a debug packet by a debug interface circuit of the IC device. The debug interface circuit authenticates the debug packet in response to the debug packet having a command code that specifies enable debug mode or a command code that specifies disable debug mode. In response to the debug packet passing authentication and the command code specifying enable, the debug interface circuit enables debug mode of the IC device. In response to the debug packet passing authentication and the command code specifying disable, the debug interface circuit disables the debug mode of the IC device. In response to the debug packet failing authentication, the debug interface circuit rejects the debug packet.
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公开(公告)号：US10776522B1
公开(公告)日：2020-09-15
申请号：US15900380
申请日：2018-02-20
Applicant: Xilinx, Inc.
Inventor： Steven E. McNeil , Jason J. Moore , Theodore A. Ennis
Abstract: Protecting circuit designs can include, in response to receiving a first encrypted public key, generating, using a hash circuit within the integrated circuit, a first hash of the first encrypted public key. The first hash can be compared with a second hash that was previously stored within a non-volatile memory of the integrated circuit. In response to determining that the first hash matches the second hash, the first encrypted public key is decrypted resulting in a first decrypted public key. A determination is made whether received configuration data for the device is authentic using the first decrypted public key.
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公开(公告)号：US09270469B2
公开(公告)日：2016-02-23
申请号：US14185780
申请日：2014-02-20
Applicant: Xilinx, Inc.
Inventor： Jason J. Moore , Steven E. McNeil , Stephen M. Trimberger
CPC classification number: H04L9/3247 , G06F21/572 , G06F21/575 , G06F21/71 , G06F21/76 , H04L9/0825 , H04L9/0891 , H04L9/3236
Abstract: One approach for authenticating data includes storing a plurality of combinations of representations of public keys and session key IDs in a non-volatile memory. A payload and accompanying public key, session key ID, and signature of the payload are input. The signature is a function of the payload and a private key of a key pair that includes the accompanying public key and the private key. Authenticity of the payload is determined based on the accompanying public key and session key ID and the combinations stored in the non-volatile memory, and from the signature and the payload. In response to determining that the payload is authentic, the payload is processed, and in response to determining that the payload is not authentic, processing of the payload is disabled.
Abstract translation: 用于认证数据的一种方法包括将公共密钥和会话密钥ID的表示的多个组合存储在非易失性存储器中。 输入有效载荷和伴随的公钥，会话密钥ID和有效载荷的签名。 签名是有效载荷和密钥对的私钥的功能，包括伴随的公钥和私钥。 基于附带的公钥和会话密钥ID以及存储在非易失性存储器中的组合，以及从签名和有效载荷来确定有效载荷的真实性。 响应于确定有效载荷是真实的，处理有效载荷，并且响应于确定有效载荷不可靠，禁用有效载荷的处理。
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