公开(公告)号：US10969433B1

公开(公告)日：2021-04-06

申请号：US16554059

申请日：2019-08-28

Applicant: XILINX, INC.

Inventor： Rambabu Nerukonda ,  Ismed D. Hartanto ,  Aaron K. Mathew

IPC: G01R31/3185 ,  G06F9/30 ,  G01R31/3177

Abstract: Apparatus and associated methods relate to compacting scan chain output responses of vectors into an on-chip multiple-input shift register (MISR) in the presence of unknown/indeterministic values X in design. In an illustrative example, a system may include a processing engine configured to generate a control signal for a MISR, and the control signal may hold information of what cycle has deterministic output response. The MISR may be configured to compact deterministic output responses of actual scan chain output responses in response to the decoded control signal and compare on-chip MISR signatures with expected MISR signatures to generate pass/fail status of the test. By using the system, unknown/indeterministic values X on the output responses may be blocked from being compacted into the MISR. Accordingly, the on-chip MISR signatures may not be corrupted by the unknown/indeterministic values X, and accuracy of the scan test may be advantageously improved.

公开(公告)号：US11755804B2

公开(公告)日：2023-09-12

申请号：US17646184

申请日：2021-12-28

Applicant: Xilinx, Inc.

Inventor： Albert Shih-Huai Lin ,  Rambabu Nerukonda ,  Niravkumar Patel ,  Amitava Majumdar

IPC: G06F30/333 ,  G06F30/367 ,  G06F30/396 ,  G06F30/398 ,  G06F30/20 ,  G06F11/267 ,  G06F11/27 ,  H01L25/00 ,  H03K19/17732 ,  H03K19/17764 ,  G06F115/08 ,  H01L21/66

CPC classification number: G06F30/333 ,  H03K19/17732 ,  H03K19/17764 ,  G06F11/267 ,  G06F11/27 ,  G06F30/20 ,  G06F30/367 ,  G06F30/396 ,  G06F30/398 ,  G06F2115/08 ,  H01L22/34 ,  H01L25/00

Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.

公开(公告)号：US20230205959A1

公开(公告)日：2023-06-29

申请号：US17646184

申请日：2021-12-28

Applicant: Xilinx, Inc.

Inventor： Albert Shih-Huai Lin ,  Rambabu Nerukonda ,  Niravkumar Patel ,  Amitava Majumdar

IPC: G06F30/333

CPC classification number: G06F30/333 ,  G06F2115/08

Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.