公开(公告)号：US09330220B1

公开(公告)日：2016-05-03

申请号：US14467908

申请日：2014-08-25

Applicant: Xilinx, Inc.

Inventor： Mehrdad E. Dehkordi ,  Marvin Tom ,  Sridhar Krishnamurthy ,  Abhishek Joshi

IPC: G06F17/50 ,  G06F1/10

CPC classification number: G06F17/5072 ,  G06F1/10 ,  G06F17/5027 ,  G06F17/5077 ,  G06F2217/62

Abstract: Clock region partitioning and clock routing includes creating partitions for a plurality of clocks of a circuit design, and legalizing the partitions using a processor according to a number of clocks in each partition and assignment of clock distribution tracks. Roots for implementing clock trees of the clocks are selected within the partitions.

Abstract translation: 时钟区域划分和时钟路由包括为电路设计的多个时钟创建分区，以及根据每个分区中的时钟数量和时钟分配轨道的分配，使用处理器对分区进行合法化。 在分区内选择实现时钟树的根。

公开(公告)号：US10068048B1

公开(公告)日：2018-09-04

申请号：US15213214

申请日：2016-07-18

Applicant: Xilinx, Inc.

Inventor： Mehrdad Eslami Dehkordi ,  Marvin Tom ,  Sridhar Krishnamurthy ,  Frank Mueller

IPC: G06F17/50

Abstract: The disclosure describes approaches for generating a clock tree for a circuit design. Initial clock trees are generated and elements are assigned to locations on an integrated circuit (IC). Each of the initial clock trees includes a clock root, a spine including the clock root, and branches connected to and extending from the spine. Each clock load is coupled to one of the branches. The clock tree further includes programmable delay circuits having initial delay values that are balanced. If the circuit design does not satisfy timing constraints, at least one clock root is moved from a respective first location to a respective second location.

公开(公告)号：US09529957B1

公开(公告)日：2016-12-27

申请号：US14606988

申请日：2015-01-27

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Xiao Dong ,  Marvin Tom

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5054

Abstract: Placing a circuit design may include partitioning circuit elements of the circuit design into circuit element sets and grouping bins of an integrated circuit into bin sets. The bins include circuit elements of the circuit design from an initial placement. Placing a circuit design also may include determining a dependency connectivity metric for the circuit elements and, using a processor, selectively relocating circuit elements concurrently, for a plurality of iterations, using a cost metric for relocating the circuit elements and using an order of processing the circuit elements determined from the bin sets, the circuit element sets, and the dependency connectivity metrics.

Abstract translation: 放置电路设计可以包括将电路设计的电路元件分成电路元件组，并将集成电路的盒分组成箱组。 该箱包括从初始放置的电路设计的电路元件。 放置电路设计还可以包括确定电路元件的依赖性连接度量，并且使用处理器，使用用于重新定位电路元件的成本度量并使用处理顺序来选择性地重新定位电路元件，用于多个迭代 从箱组确定的电路元件，电路元件组和依赖性连接度量。

公开(公告)号：US10042971B1

公开(公告)日：2018-08-07

申请号：US15210756

申请日：2016-07-14

Applicant: Xilinx, Inc.

Inventor： Mehrdad Eslami Dehkordi ,  Raoul Badaoui ,  Marvin Tom ,  Sridhar Krishnamurthy

IPC: G06F17/50

Abstract: Approaches for routing clock signals of a circuit design on an IC include determining initial partitions of clock sources and clock loads. Each initial partition includes one of the clock sources and a subset of the clock loads associated with the one clock source, and initial each partition defines an area of the IC in which the one of the clock sources and the associated subset of clock loads are placed. A processor determines for each of the initial partitions, whether or not the initial partition has a congested clock region. For each initial partition determined to have a congested clock region, the processor defines a respective new partition by excluding the one of the clock sources from the new partition. The new partition includes the subset of the clock loads and does not include the one clock source. The processor then routes clock signals from the clock sources to the clock loads.