公开(公告)号：US08743559B1

公开(公告)日：2014-06-03

申请号：US13764108

申请日：2013-02-11

Applicant: Xilinx, Inc.

Inventor： Paul Y. Wu ,  Richard L. Wheeler

IPC: H05K7/00

CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L23/5286 ,  H01L2224/16 ,  H01L2924/15311

Abstract: An interconnect array is described. The interconnect array comprises a pattern of adjacent interconnect tiles, each interconnect tile comprising ten interconnect locations including eight I/O signal connectivity locations forming a perimeter array having a corner I/O signal connectivity location, a center connectivity location surrounded by the eight I/O signal connectivity locations in the perimeter array being a first ground connectivity location or a power connectivity location, and a second ground connectivity location adjacent to the corner I/O signal connectivity location of the perimeter array and externally offset from the perimeter array to form an asymmetrically shaped interconnect tile. At least one interconnect tile of the pattern of adjacent interconnect tiles has a center connectivity location that is a power connectivity location.

Abstract translation: 描述互连阵列。 互连阵列包括相邻互连瓦片的图案，每个互连瓦片包括十个互连位置，包括形成具有拐角I / O信号连接位置的周边阵列的八个I / O信号连接位置，由八个I / 周边阵列中的O信号连接位置是第一地面连接位置或电力连接位置，以及与周边阵列的角I / O信号连接位置相邻的第二接地连接位置，并且在外部偏离周界阵列以形成 不对称形状的互连瓦片。 相邻互连瓦片的图案的至少一个互连瓦片具有作为功率连接位置的中心连接位置。