公开(公告)号：US20150282299A1

公开(公告)日：2015-10-01

申请号：US14242795

申请日：2014-04-01

Applicant: XILINX, INC.

Inventor： Hong Shi ,  Paul Y. Wu ,  Jian Tu

IPC: H05K1/02

CPC classification number: H01L23/66 ,  H01L23/49827 ,  H01L24/16 ,  H01L2223/6627 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19107

Abstract: Embodiments of the invention generally provide an electronic device comprising an electrical interconnect component that includes an electrical trace. The electrical trace has geometric characteristics that serve to suppress the skin effect over a large band of frequency components. More specifically, the electrical trace has a thickness that is less than a skin depth for a particular chosen frequency component. By making the electrical trace have a thickness that is less than the skin depth, the current flows through substantially the entire cross-sectional area of the electrical trace for all frequencies up to the chosen frequency component, which reduces the effects associated with the skin effect.

Abstract translation: 本发明的实施例通常提供一种包括电互连部件的电子设备，其包括电迹线。 电迹线具有几何特征，其用于抑制大频带组件的皮肤效应。 更具体地，电迹线具有小于特定选定频率分量的趋肤深度的厚度。 通过使电迹线具有小于皮肤深度的厚度，电流流过所有频率的电迹线的整个横截面积直到选定的频率分量，这降低了与皮肤效应相关的影响 。

公开(公告)号：US09006030B1

公开(公告)日：2015-04-14

申请号：US14100678

申请日：2013-12-09

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam ,  Paul Y. Wu ,  Manoj Nachnani

IPC: H01L23/492 ,  H01L21/58 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: An integrated circuit includes a stacked conductive layer interposer and a first die at least partially encapsulated in a mold material. The first die is mechanically and electrically attached to a top surface of the stacked conductive layer interposer using solder bumps. The integrated circuit further includes a first warpage correction layer.

Abstract translation: 集成电路包括层叠的导电层插入件和至少部分地封装在模具材料中的第一模具。 使用焊料凸块将第一裸片机械和电连接到堆叠的导电层插入件的顶表面。 集成电路还包括第一翘曲校正层。

公开(公告)号：US20140262440A1

公开(公告)日：2014-09-18

申请号：US13827048

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Namhoon Kim ,  Joong-Ho Kim ,  Suresh Ramalingam ,  Paul Y. Wu ,  Woon-Seong Kwon ,  Dennis C.P. Leung

IPC: H05K1/02

CPC classification number: H05K1/02 ,  H01L23/49822 ,  H01L23/66 ,  H01L2224/16225

Abstract: A multi-layer core organic package substrate includes: a multi-layer core comprising at least two organic core layers, wherein two of the at least two organic core layers are separated by a core metal layer; a first plurality of build-up layers formed on top of the multi-core layer; and a second plurality of build-up layers formed below the multi-core layer.

Abstract translation: 多层核心有机封装基板包括：包含至少两个有机芯层的多层芯，其中所述至少两个有机芯层中的两个被芯金属层分隔开; 形成在所述多芯层的顶部上的第一多个堆积层; 以及形成在所述多芯层下方的第二多个积聚层。

公开(公告)号：US08743559B1

公开(公告)日：2014-06-03

申请号：US13764108

申请日：2013-02-11

Applicant: Xilinx, Inc.

Inventor： Paul Y. Wu ,  Richard L. Wheeler

IPC: H05K7/00

CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L23/5286 ,  H01L2224/16 ,  H01L2924/15311

Abstract: An interconnect array is described. The interconnect array comprises a pattern of adjacent interconnect tiles, each interconnect tile comprising ten interconnect locations including eight I/O signal connectivity locations forming a perimeter array having a corner I/O signal connectivity location, a center connectivity location surrounded by the eight I/O signal connectivity locations in the perimeter array being a first ground connectivity location or a power connectivity location, and a second ground connectivity location adjacent to the corner I/O signal connectivity location of the perimeter array and externally offset from the perimeter array to form an asymmetrically shaped interconnect tile. At least one interconnect tile of the pattern of adjacent interconnect tiles has a center connectivity location that is a power connectivity location.

Abstract translation: 描述互连阵列。 互连阵列包括相邻互连瓦片的图案，每个互连瓦片包括十个互连位置，包括形成具有拐角I / O信号连接位置的周边阵列的八个I / O信号连接位置，由八个I / 周边阵列中的O信号连接位置是第一地面连接位置或电力连接位置，以及与周边阵列的角I / O信号连接位置相邻的第二接地连接位置，并且在外部偏离周界阵列以形成 不对称形状的互连瓦片。 相邻互连瓦片的图案的至少一个互连瓦片具有作为功率连接位置的中心连接位置。

公开(公告)号：US10038259B2

公开(公告)日：2018-07-31

申请号：US14174697

申请日：2014-02-06

Applicant: Xilinx, Inc.

Inventor： Paul Y. Wu ,  Sarajuddin Niazi ,  Raymond E. Anderson ,  Suresh Ramalingam

IPC: H05K1/11 ,  H05K1/14 ,  H01R12/71 ,  H01R43/02 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01R12/71 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16 ,  H01L2924/0002 ,  H01R43/0235 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

公开(公告)号：US20150222033A1

公开(公告)日：2015-08-06

申请号：US14174697

申请日：2014-02-06

Applicant: Xilinx, Inc.

Inventor： Paul Y. Wu ,  Sarajuddin Niazi ,  Raymond E. Anderson ,  Suresh Ramlingam

IPC: H01R12/71 ,  H01R43/02

CPC classification number: H01R12/71 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16 ,  H01L2924/0002 ,  H01R43/0235 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

Abstract translation: 用于放置在封装和集成电路板之间的装置包括：插入件，其具有：具有顶侧和底侧的基板; 在衬底的顶侧的第一组衬垫; 在衬底的底侧的第二组衬垫; 以及衬底中的多个通孔，将第一组中的各个焊盘连接到第二组中的相应焊盘的通孔; 其中插入件的厚度小于封装和集成电路板之间的间隔。

公开(公告)号：US20150187715A1

公开(公告)日：2015-07-02

申请号：US14659154

申请日：2015-03-16

Applicant: XILINX, INC.

Inventor： Michael J. Hart ,  Jan L. de Jong ,  Paul Y. Wu

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/556 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05567 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1191 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/1355 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/36 ,  H01L2224/05552

Abstract: A semiconductor device includes a first under-bump metallization (UBM) layer disposed over a bond pad, a dielectric layer above an interconnect layer having a via exposing at least a portion of the first UBM layer. A second UBM layer is disposed above the first UBM layer and forms a UBM bucket over the via. The first UBM layer and UBM bucket are configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.

Abstract translation: 半导体器件包括布置在接合焊盘上的第一凸点下金属化（UBM）层，在互连层上方的电介质层，其具有暴露第一UBM层的至少一部分的通孔。 第二UBM层设置在第一UBM层之上并在通孔上形成UBM桶。 第一UBM层和UBM桶被配置为支撑焊球，并且可以有利地阻挡具有相关入射角的焊球发射的所有α粒子到达IC的有源半导体区域。 因此，减少或消除了诸如存储器单元中的单个事件的混乱的软错误。