公开(公告)号：US11475199B1

公开(公告)日：2022-10-18

申请号：US17486547

申请日：2021-09-27

Applicant: Xilinx, Inc.

Inventor： Saikat Bandyopadhyay ,  Feng Cai ,  Tapodyuti Mandal ,  Vinayak Thonda ,  Sree Rohith Pulipaka

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/3308 ,  G06F117/08

Abstract: Simulating a circuit design using a data processing system includes partitioning the circuit design into a top-level design and a sub-design along a boundary defined by one or more stream channels coupling a component of the top-level design with the sub-design. The sub-design is extracted from the circuit design and replaced with a stub having a client socket. A wrapper having a server socket is added to the sub-design. The top-level design and the sub-design are compiled into respective simulation kernels. The circuit design is simulated by executing the respective simulation kernels concurrently. The respective kernels communicate over a socket connection established by the client socket and the server socket. In other aspects, the partitioning results in partitions such that one partition is simulated as software and another partition is implemented in circuitry such that the circuit design may be hardware co-simulated.