公开(公告)号：US10726182B1

公开(公告)日：2020-07-28

申请号：US16100041

申请日：2018-08-09

Applicant: Xilinx, Inc.

Inventor： Sandeep S. Deshpande ,  Feng Cai ,  Saikat Bandyopadhyay

IPC: G06F17/50 ,  G06F30/3312 ,  G06F9/448 ,  G06F30/327

Abstract: Disclosed approaches involve simulating a circuit design specified in a hardware description language (HDL). During simulation, a thread is started at an edge of a simulation clock signal for evaluation of states of a finite state machine (FSM) that represent a series of events specified in a statement in the HDL. The thread transitions from one state to a next state in the FSM in response to evaluation of the one state. In response to encountering a fork state in the FSM, the thread is forked into two threads during simulation. The fork state represents a composite operator in the statement, and the FSM has a branch from the fork state for each operand of the composite operator. In response to encountering a join state in the FSM by the two threads, the two threads are joined into one thread.

公开(公告)号：US10671785B1

公开(公告)日：2020-06-02

申请号：US15370339

申请日：2016-12-06

Applicant: Xilinx, Inc.

Inventor： Valeria Mihalache ,  Kumar Deepak ,  Saikat Bandyopadhyay ,  Sandeep S. Deshpande ,  Feng Cai

IPC: G06F30/367

Abstract: Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.

公开(公告)号：US11475199B1

公开(公告)日：2022-10-18

申请号：US17486547

申请日：2021-09-27

Applicant: Xilinx, Inc.

Inventor： Saikat Bandyopadhyay ,  Feng Cai ,  Tapodyuti Mandal ,  Vinayak Thonda ,  Sree Rohith Pulipaka

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/3308 ,  G06F117/08

Abstract: Simulating a circuit design using a data processing system includes partitioning the circuit design into a top-level design and a sub-design along a boundary defined by one or more stream channels coupling a component of the top-level design with the sub-design. The sub-design is extracted from the circuit design and replaced with a stub having a client socket. A wrapper having a server socket is added to the sub-design. The top-level design and the sub-design are compiled into respective simulation kernels. The circuit design is simulated by executing the respective simulation kernels concurrently. The respective kernels communicate over a socket connection established by the client socket and the server socket. In other aspects, the partitioning results in partitions such that one partition is simulated as software and another partition is implemented in circuitry such that the circuit design may be hardware co-simulated.

公开(公告)号：US09582619B1

公开(公告)日：2017-02-28

申请号：US14058505

申请日：2013-10-21

Applicant: Xilinx, Inc.

Inventor： David K. Liddell ,  Feng Cai ,  Saikat Bandyopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5045

Abstract: An approach for simulating a block of a circuit design includes using a row-matching table and a port state vector. The row-matching table includes a plurality of rows, and each row includes encoded input match patterns corresponding to a plurality of input ports of the block and an associated output value. The port state vector includes input state codes associated with the input ports. In response to an update of an input signal value at one of the input ports during simulation, the input state code associated with the one input port is updated according to the updated input signal value. A bit-to-bit pattern match is performed for each bit in the port state vector to a corresponding bit in the encoded input match patterns in one or more rows of the row-matching table. The associated output value of a matching row is selected as a new output value.

Abstract translation: 用于模拟电路设计的块的方法包括使用行匹配表和端口状态向量。 行匹配表包括多行，并且每行包括与块的多个输入端口对应的编码输入匹配模式和相关联的输出值。 端口状态向量包括与输入端口相关联的输入状态代码。 响应于在模拟期间在输入端口之一处的输入信号值的更新，与一个输入端口相关联的输入状态代码根据更新的输入信号值被更新。 对端口状态向量中的每个位执行位对位模式匹配，使其与行匹配表的一行或多行中的编码输入匹配模式中的相应位相对应。 匹配行的关联输出值被选为新的输出值。