公开(公告)号：US10482054B1

公开(公告)日：2019-11-19

申请号：US15261626

申请日：2016-09-09

Applicant: Xilinx, Inc.

Inventor： Ling Liu ,  Michaela Blott ,  Kimon Karras ,  Thomas Janson ,  Kornelis A. Vissers

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  H04L12/861

Abstract: The coherent accelerator processor interface (CAPI) provides a high-performance when using heterogeneous compute architectures, but CAPI is not compatible with the advanced extensible interface (AXI) which is used by many accelerators. The examples herein describe an AXI-CAPI adapter (e.g., a hardware architecture) that converts AXI signals to CAPI signals and vice versus. In one example, the AXI-CAPI adapter includes four modules: a low-level shim, a high-level shim, an AXI full module, and an AXI Lite module which are organized in a hierarchy of hardware elements. Each of the modules outputs can output a different version of the AXI signals using the hierarchical structure.