中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.013 seconds)

    Sparse matrix processing circuitry
    1.
    发明授权
    Sparse matrix processing circuitry 有权

    公开(公告)号：US10572409B1

    公开(公告)日：2020-02-25

    申请号：US15976722

    申请日：2018-05-10

    Applicant: Xilinx, Inc.

    Inventor： Jindrich Zejda ,  Ling Liu ,  Yifei Zhou ,  Ashish Sirasao

    IPC: G06F3/00 ,  G06F5/00 ,  G06F13/20 ,  G06N3/08

    Abstract: A memory arrangement can store a matrix of matrix data elements specified as index-value pairs that indicate row and column indices and associated values. First split-and-merge circuitry is coupled between the memory arrangement and a first set of FIFO buffers for reading the matrix data elements from the memory arrangement and putting the matrix data elements in the first set of FIFO buffers based on column indices. A pairing circuit is configured to read vector data elements, pair the vector data elements with the matrix data elements, and put the paired matrix and vector data elements in a second set of FIFO buffers based on column indices. Second split-and-merge circuitry is configured to read paired matrix and vector data elements from the second set of FIFO buffers and put the paired matrix and vector data elements in a third set of FIFO buffers based on row indices.

    AXI-CAPI adapter
    2.
    发明授权
    AXI-CAPI adapter 有权

    公开(公告)号：US10482054B1

    公开(公告)日：2019-11-19

    申请号：US15261626

    申请日：2016-09-09

    Applicant: Xilinx, Inc.

    Inventor： Ling Liu ,  Michaela Blott ,  Kimon Karras ,  Thomas Janson ,  Kornelis A. Vissers

    IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  H04L12/861

    Abstract: The coherent accelerator processor interface (CAPI) provides a high-performance when using heterogeneous compute architectures, but CAPI is not compatible with the advanced extensible interface (AXI) which is used by many accelerators. The examples herein describe an AXI-CAPI adapter (e.g., a hardware architecture) that converts AXI signals to CAPI signals and vice versus. In one example, the AXI-CAPI adapter includes four modules: a low-level shim, a high-level shim, an AXI full module, and an AXI Lite module which are organized in a hierarchy of hardware elements. Each of the modules outputs can output a different version of the AXI signals using the hierarchical structure.

    Sparse matrix processing circuitry
    4.
    发明授权
    Sparse matrix processing circuitry 有权

    公开(公告)号：US10936311B1

    公开(公告)日：2021-03-02

    申请号：US16505987

    申请日：2019-07-09

    Applicant: Xilinx, Inc.

    Inventor： Ling Liu ,  Yifei Zhou ,  Xiao Teng ,  Ashish Sirasao ,  Chuanhua Song ,  Aaron Ng

    IPC: G06F9/30 ,  G06F17/16

    Abstract: Disclosed approaches for multiplying a sparse matrix by dense a vector or matrix include first memory banks for storage of column indices, second memory banks for storage of row indices, and third memory banks for storage of non-zero values of a sparse matrix. A pairing circuit distributes an input stream of vector elements across first first-in-first-out (FIFO) buffers according to the buffered column indices. Multiplication circuitry multiplies vector elements output from the first FIFO buffers by corresponding ones of the non-zero values from the third memory banks, and stores products in second FIFO buffers. Row-aligner circuitry organize the products output from the second FIFO buffers into third FIFO buffers according to row indices in the second memory banks. Accumulation circuitry accumulates respective totals from products output from the third FIFO buffers.

    Pipelined database processing circuit and method
    5.
    发明授权
    Pipelined database processing circuit and method 有权

    公开(公告)号：US10482129B1

    公开(公告)日：2019-11-19

    申请号：US15484455

    申请日：2017-04-11

    Applicant: Xilinx, Inc.

    Inventor： Michaela Blott ,  Ling Liu ,  Daniel Ziener ,  Kimon Karras

    IPC: G06F7/02 ,  G06F16/00 ,  G06F16/9038 ,  G06F3/06 ,  G06F16/93 ,  G06F16/901 ,  G06F16/903

    Abstract: Disclosed approaches for accessing data involve determining in a first stage of a pipelined processing circuit, hash values from keys in a data access request and determining in a second stage of the pipelined processing circuit and from a hash table, addresses associated with the hash values. In a third stage of the pipelined processing circuit, data are read at the addresses in a memory arrangement, and in a fourth stage of the pipelined processing circuit a subset of the data read from the memory arrangement is selected according to a query in the data access request. In a fifth stage of the pipelined processing circuit, the subset of the data read from the memory arrangement is merged into response data.

    MEMORY ARRANGEMENT FOR IMPLEMENTATION OF HIGH-THROUGHPUT KEY-VALUE STORES
    7.
    发明申请
    MEMORY ARRANGEMENT FOR IMPLEMENTATION OF HIGH-THROUGHPUT KEY-VALUE STORES 有权
    用于实施高价值重要价值存储的内存安排

    公开(公告)号：US20150160862A1

    公开(公告)日：2015-06-11

    申请号：US14100250

    申请日：2013-12-09

    Applicant: Xilinx, Inc.

    Inventor： Michaela Blott ,  Ling Liu ,  Kornelis A. Vissers

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/466 ,  G06F12/00 ,  G06F13/00 ,  G06F17/30221 ,  G06F17/30312 ,  G06F17/30519

    Abstract: A circuit for processing data is described. The circuit comprises an input for receiving a request for implementing a key-value store data transaction; a plurality of memory interfaces associated with different memory types enabling access to a plurality of memory devices associated with a key-value store; and a memory management circuit controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion.

    Abstract translation: 描述用于处理数据的电路。 电路包括用于接收实现键值存储数据事务的请求的输入; 与能够访问与键值存储相关联的多个存储器件的不同存储器类型相关联的多个存储器接口; 以及存储器管理电路，其基于数据传输标准，通过多个存储器接口来控制数据的路由。

    CIRCUITS FOR AND METHODS OF CONTROLLING THE OPERATION OF A HYBRID MEMORY SYSTEM
    8.
    发明申请
    CIRCUITS FOR AND METHODS OF CONTROLLING THE OPERATION OF A HYBRID MEMORY SYSTEM 有权
    用于控制混合存储器系统的操作的电路和方法

    公开(公告)号：US20160217835A1

    公开(公告)日：2016-07-28

    申请号：US14607978

    申请日：2015-01-28

    Applicant: Xilinx, Inc.

    Inventor： Michaela Blott ,  Ling Liu ,  Kornelis A. Vissers

    IPC: G11C7/10 ,  G06F12/02 ,  G06F12/08

    CPC classification number: G11C7/1057 ,  G06F12/0246 ,  G06F12/0813 ,  G06F13/1694 ,  G06F2212/7203 ,  G11C7/1072

    Abstract: A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer coupled to the second memory to compensate for a difference in the first access time and the second access time; and a circuit for merging outputs of the first memory and delayed outputs of the second memory to generate ordered output data. A method of controlling the operation of a memory system is also disclosed.

    Abstract translation: 描述用于控制具有不同类型的存储器的存储器系统的操作的电路。 该电路包括具有第一类型的存储元件并且具有第一存取时间的第一存储器; 具有第二类型的存储元件并具有第二存取时间的第二存储器，其中所述第二类型的存储元件不同于所述第一类型的存储元件; 存储器控制电路，其能够访问第一存储器和第二存储器; 延迟缓冲器，其耦合到所述第二存储器，以补偿所述第一访问时间和所述第二访问时间的差异; 以及用于合并第一存储器的输出和第二存储器的延迟输出的电路，以产生有序的输出数据。 还公开了一种控制存储器系统的操作的方法。

Patent Agency Ranking