公开(公告)号：US10657084B1

公开(公告)日：2020-05-19

申请号：US16183646

申请日：2018-11-07

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Darren Jue ,  Tao Yu ,  Kushagra Sharma ,  Tuan Van-Dinh

IPC: G06F13/24 ,  G06F13/28

Abstract: A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.