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    CUSTOMIZABLE MULTI QUEUE DMA INTERFACE
    1.
    发明申请
    CUSTOMIZABLE MULTI QUEUE DMA INTERFACE 审中-公开

    公开(公告)号：US20190243781A1

    公开(公告)日：2019-08-08

    申请号：US15892266

    申请日：2018-02-08

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S Thyamagondlu ,  Darren Jue ,  Tao Yu ,  John West ,  Hanh Hoang ,  Ravi Sunkavalli

    IPC: G06F12/1081

    CPC classification number: G06F12/1081 ,  G06F2212/621 ,  G06F2213/28

    Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

    DESCRIPTOR CACHE EVICTION FOR MULTI-QUEUE DIRECT MEMORY ACCESS
    2.
    发明公开
    DESCRIPTOR CACHE EVICTION FOR MULTI-QUEUE DIRECT MEMORY ACCESS 审中-公开

    公开(公告)号：US20240330191A1

    公开(公告)日：2024-10-03

    申请号：US18191326

    申请日：2023-03-28

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S. Thyamagondlu ,  Tao Yu

    IPC: G06F12/0891

    CPC classification number: G06F12/0891 ,  G06F2212/27

    Abstract: Evicting queues from a memory of a direct memory access system includes monitoring a global eviction timer. From a plurality of descriptor lists stored in a plurality of entries of a cache memory, a set of candidate descriptor lists is determined. The set of candidate descriptor lists includes one or more of the plurality of descriptor lists in a prefetch only state. An eviction event can be detected by detecting a first eviction condition including a state of the global eviction timer and a second eviction condition. In response to detecting the eviction event, a descriptor list from the set of candidate descriptor lists is selected for eviction. The selected descriptor list can be evicted from the cache memory.

    Customizable multi queue DMA interface
    4.
    发明授权
    Customizable multi queue DMA interface 有权

    公开(公告)号：US10983920B2

    公开(公告)日：2021-04-20

    申请号：US15892266

    申请日：2018-02-08

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S Thyamagondlu ,  Darren Jue ,  Tao Yu ,  John West ,  Hanh Hoang ,  Ravi Sunkavalli

    IPC: G06F12/1081

    Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

    Interrupt moderation and aggregation circuitry
    5.
    发明授权
    Interrupt moderation and aggregation circuitry 有权

    公开(公告)号：US10657084B1

    公开(公告)日：2020-05-19

    申请号：US16183646

    申请日：2018-11-07

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S. Thyamagondlu ,  Darren Jue ,  Tao Yu ,  Kushagra Sharma ,  Tuan Van-Dinh

    IPC: G06F13/24 ,  G06F13/28

    Abstract: A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.

    Descriptor fetching for a multi-queue direct memory access system
    6.
    发明授权
    Descriptor fetching for a multi-queue direct memory access system 有权

    公开(公告)号：US12259833B2

    公开(公告)日：2025-03-25

    申请号：US18191365

    申请日：2023-03-28

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S. Thyamagondlu ,  Tao Yu ,  Chiranjeevi Sirandas ,  Nicholas Trank

    IPC: G06F13/28

    Abstract: Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.

    DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM
    7.
    发明公开
    DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM 审中-公开

    公开(公告)号：US20240330215A1

    公开(公告)日：2024-10-03

    申请号：US18191365

    申请日：2023-03-28

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S. Thyamagondlu ,  Tao Yu ,  Chiranjeevi Sirandas ,  Nicholas Trank

    IPC: G06F13/28

    CPC classification number: G06F13/28

    Abstract: Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.

    MULTI-HOST DIRECT MEMORY ACCESS SYSTEM FOR INTEGRATED CIRCUITS
    8.
    发明申请
    MULTI-HOST DIRECT MEMORY ACCESS SYSTEM FOR INTEGRATED CIRCUITS 有权

    公开(公告)号：US20220092010A1

    公开(公告)日：2022-03-24

    申请号：US17457576

    申请日：2021-12-03

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S. Thyamagondlu ,  Darren Jue ,  Ravi Sunkavalli ,  Akhil Krishnan ,  Tao Yu ,  Kushagra Sharma

    IPC: G06F13/28 ,  G06F13/24

    Abstract: A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.

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