公开(公告)号：US10437949B1

公开(公告)日：2019-10-08

申请号：US15676104

申请日：2017-08-14

Applicant: Xilinx, Inc.

Inventor： Valeria Mihalache ,  Kumar Deepak ,  Saikat Bandyopadhyay

IPC: G06F9/455 ,  G06F17/50

Abstract: Simulating a circuit design can include detecting, using a processor, an assignment for a signal of a circuit design during a delta cycle of a simulation of the circuit design and comparing, using the processor, a range of the assignment for the signal with a range of an existing event for the signal for the delta cycle. In response to determining that the range of the assignment for the signal and the range of the existing event meet a condition, the existing event is updated, using the processor, resulting in a merged event. The merged event is scheduled for execution for the delta cycle using the processor.

公开(公告)号：US10671785B1

公开(公告)日：2020-06-02

申请号：US15370339

申请日：2016-12-06

Applicant: Xilinx, Inc.

Inventor： Valeria Mihalache ,  Kumar Deepak ,  Saikat Bandyopadhyay ,  Sandeep S. Deshpande ,  Feng Cai

IPC: G06F30/367

Abstract: Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.

公开(公告)号：US09619601B1

公开(公告)日：2017-04-11

申请号：US14603259

申请日：2015-01-22

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Valeria Mihalache

IPC: G06F17/50 ,  G06F9/44

CPC classification number: G06F17/5045 ,  G06F8/30 ,  G06F8/35 ,  G06F17/5009 ,  G06F17/5022

Abstract: An example method of generating a control and data flow graph for hardware description language (HDL) code specifying a circuit design is described. The method includes traversing an abstract syntax tree (AST) representation of the HDL code having a plurality of modules on a module-by-module basis. The method further includes adding an execution unit to the control and data flow graph for each module having concurrent paths. Each execution unit includes nodes in the control and data flow graph. The nodes include a loopback sink that merges the concurrent paths and a loopback source that receives feedback from the loopback sink and propagates the feedback to the concurrent paths.