公开(公告)号：US09774866B1

公开(公告)日：2017-09-26

申请号：US14639405

申请日：2015-03-05

Applicant: Xilinx, Inc.

Inventor： Venkata V. Dhanikonda ,  Arun Ananthapadmanaban

IPC: H04N19/146 ,  H04N7/12 ,  H04L12/861

CPC classification number: H04N19/146 ,  G09G5/006 ,  G09G5/008 ,  G09G5/12 ,  G09G2320/0693 ,  G09G2320/08 ,  G09G2370/10 ,  H04L7/0012 ,  H04L25/14 ,  H04L49/90 ,  H04N7/12 ,  H04N21/4305

Abstract: A video processing system can include a buffer, a packetizer block that is coupled to the buffer, and a buffer controller that is coupled to the buffer and the packetizer block. The buffer is capable of receiving and storing a video signal as video data. The packetizer block is capable of packetizing video data read from the buffer and sending packetized data to a node external to the video processing system. The buffer controller is capable of controlling an amount of video data included within each packet generated by the packetizer block.

公开(公告)号：US10990826B1

公开(公告)日：2021-04-27

申请号：US16358930

申请日：2019-03-20

Applicant: Xilinx, Inc.

Inventor： Mujib Haider ,  Venkata V. Dhanikonda ,  Ashish Sirasao

IPC: G06K9/00 ,  G06F17/15 ,  G06T7/246 ,  G06N3/04

Abstract: Detecting objects in video may include receiving object detections for a plurality of selected frames of a video from a still image detector, wherein the plurality of selected frames are non-adjacent frames of the video, propagating the object detections from the plurality of selected frames to sequential frames of the video adjacent to the plurality of selected frames based on a distance metric and vector flow data for the sequential frames, suppressing false positive object detections from the propagating, and outputting resulting object detections for the sequential frames of the video.

公开(公告)号：US11245915B1

公开(公告)日：2022-02-08

申请号：US17025062

申请日：2020-09-18

Applicant: Xilinx, Inc.

Inventor： Mujib Haider ,  Venkata V. Dhanikonda

IPC: H04N19/423 ,  H04N19/186 ,  H04N19/132 ,  H04N19/176 ,  H04N19/136

Abstract: Disclosed approaches for converting between block coded format and raster format include buffers for first type component blocks and second type component blocks of a frame. The buffers are sized less than the width of the frame. A demultiplexer circuit is configured to input the first type component blocks and the second type component blocks in coded block order, and enable storage of the first type component blocks in the first buffer and of the second type component blocks in the second buffer in the coded block order. A multiplexer circuit is configured to flush data from the first buffer in raster scan order in response to a completed set of the first type component blocks in the first buffer, and flush data from the second buffer in raster scan order in response to a completed set of the second type component blocks in the second buffer.