公开(公告)号：US09405871B1

公开(公告)日：2016-08-02

申请号：US14562359

申请日：2014-12-05

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri ,  Vinod K. Nakkala ,  Atul Srinivasan ,  Sudip K. Nag

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081

Abstract: Determining delays of paths in a circuit design includes determining whether or not each path of the plurality of paths matches a path definition of a plurality of path definitions in a path database. For each path that matches a path definition, a first path delay value associated with the matching path definition is read from the path database and associated with the matching path of the circuit design. For each path that does not match any of the path definitions, respective element delay values of elements of the path are read from an element database. A second path delay value of the non-matching path is computed as a function of the respective element delay values, and the second path delay value is associated with the path. The first and second path delay values are output along with information indicating the associated paths.

Abstract translation: 确定电路设计中的路径的延迟包括确定多个路径中的每个路径是否与路径数据库中的多个路径定义的路径定义相匹配。 对于与路径定义匹配的每个路径，从路径数据库读取与匹配路径定义相关联的第一路径延迟值，并与电路设计的匹配路径相关联。 对于不匹配任何路径定义的每个路径，从元素数据库读取路径元素的相应元素延迟值。 根据相应的元件延迟值计算非匹配路径的第二路径延迟值，并且第二路径延迟值与路径相关联。 第一和第二路径延迟值与指示相关联的路径的信息一起被输出。