公开(公告)号：US10528697B1

公开(公告)日：2020-01-07

申请号：US15818436

申请日：2017-11-20

Applicant: Xilinx, Inc.

Inventor： Wei Chen ,  Xiaojian Yang ,  Sabyasachi Das

IPC: G06F17/50

Abstract: Embodiments disclosed herein describe techniques for moving nets between a source and a plurality of sinks in a design of an integrated circuit from a data network to a clock network. In one embodiment, the clock network propagates clock signals or timing signals throughout the integrated circuit while the data network transmits data signals between circuitry in the integrated circuit. In one embodiment, the clock network has a predefined number of clock signal nets which can be assigned to carry clock signals to circuit logic in the integrated circuit. However, some of the clock signal nets may be unused. In one embodiment, a design application identifies candidate sinks which have positive slack. If using the clock network to couple the sink to the source satisfies predetermined timing requirements, then the design change is committed.