公开(公告)号：US10756019B1

公开(公告)日：2020-08-25

申请号：US16201663

申请日：2018-11-27

Applicant: Xilinx, Inc.

Inventor： Shuxian Wu ,  Xiaobao Wang ,  Xuemei Xi

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/18 ,  H01L25/04

Abstract: A die-to-die interconnect structure includes an interconnect network including a plurality of metal interconnect layers. The interconnect network is configured to electrically couple a first die and a second die mounted on a top surface of the die-to-die interconnect structure. A first metal interconnect layer of the plurality of metal interconnect layers includes a plurality of ground lines and a plurality of signal lines distributed across the first metal interconnect layer according to a GSSG pattern. In some examples, adjacent signal lines within the first metal interconnect layer are separated by a dielectric region. In some embodiments, a second metal interconnect layer of the plurality of metal interconnect layers is disposed above the first metal interconnect layer and includes a plurality of configurable signal/ground lines. By way of example, each of the plurality of configurable signal/ground lines is disposed over the dielectric region and within the second metal interconnect layer.