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    CAPACITOR STRUCTURE IN AN INTEGRATED CIRCUIT
    1.
    发明申请
    CAPACITOR STRUCTURE IN AN INTEGRATED CIRCUIT 有权
    集成电路中的电容结构

    公开(公告)号：US20160049393A1

    公开(公告)日：2016-02-18

    申请号：US14460292

    申请日：2014-08-14

    Applicant: XILINX, INC.

    Inventor： Jing Jing ,  Shuxian Wu

    IPC: H01L27/08 ,  H01L49/02

    CPC classification number: H01L27/0805 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an example, a capacitor in an integrated circuit (IC), includes: a first finger capacitor formed in at least one layer of the IC having a first bus and a second bus; a second finger capacitor formed in the at least one layer of the IC having a first bus and a second bus, where a longitudinal edge of the second bus of the second finger capacitor is adjacent a longitudinal edge of the first bus of the first finger capacitor and separated by a dielectric gap; and a first metal segment formed on a first layer above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor.

    Abstract translation: 在一个示例中，集成电路（IC）中的电容器包括：形成在具有第一总线和第二总线的IC的至少一个层中的第一指状电容器; 形成在具有第一总线和第二总线的IC的至少一层中的第二手指电容器，其中第二指状电容器的第二总线的纵向边缘与第一指状电容器的第一总线的纵向边缘相邻 并由电介质间隙隔开; 以及形成在所述至少一层上方的第一层上的第一金属段，所述第一金属段电耦合到所述第一指状电容器的第一总线，并增加所述第一指状电容器的第一总线的宽度和高度。

    SUBSTRATE NOISE ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES
    2.
    发明申请
    SUBSTRATE NOISE ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20180083096A1

    公开(公告)日：2018-03-22

    申请号：US15272292

    申请日：2016-09-21

    Applicant: Xilinx, Inc.

    Inventor： Jing Jing ,  Shuxian Wu ,  Jane Sowards

    IPC: H01L29/06 ,  H01L21/761

    CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L21/823481

    Abstract: An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

    Inductor design in active 3D stacking technology
    3.
    发明授权
    Inductor design in active 3D stacking technology 有权

    公开(公告)号：US11043470B2

    公开(公告)日：2021-06-22

    申请号：US16694476

    申请日：2019-11-25

    Applicant: XILINX, INC.

    Inventor： Jing Jing ,  Shuxian Wu ,  Xin X. Wu ,  Yohan Frans

    IPC: H01L25/065 ,  H01L23/64 ,  H01L23/522 ,  H01L25/00 ,  H01L49/02 ,  H01L21/48 ,  H01L23/538

    Abstract: Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

    Systems providing interposer structures
    4.
    发明授权
    Systems providing interposer structures 有权

    公开(公告)号：US10756019B1

    公开(公告)日：2020-08-25

    申请号：US16201663

    申请日：2018-11-27

    Applicant: Xilinx, Inc.

    Inventor： Shuxian Wu ,  Xiaobao Wang ,  Xuemei Xi

    IPC: H01L23/538 ,  H01L23/00 ,  H01L25/18 ,  H01L25/04

    Abstract: A die-to-die interconnect structure includes an interconnect network including a plurality of metal interconnect layers. The interconnect network is configured to electrically couple a first die and a second die mounted on a top surface of the die-to-die interconnect structure. A first metal interconnect layer of the plurality of metal interconnect layers includes a plurality of ground lines and a plurality of signal lines distributed across the first metal interconnect layer according to a GSSG pattern. In some examples, adjacent signal lines within the first metal interconnect layer are separated by a dielectric region. In some embodiments, a second metal interconnect layer of the plurality of metal interconnect layers is disposed above the first metal interconnect layer and includes a plurality of configurable signal/ground lines. By way of example, each of the plurality of configurable signal/ground lines is disposed over the dielectric region and within the second metal interconnect layer.

    INDUCTOR STRUCTURE WITH PRE-DEFINED CURRENT RETURN
    5.
    发明申请
    INDUCTOR STRUCTURE WITH PRE-DEFINED CURRENT RETURN 有权
    具有预定义电流返回的电感结构

    公开(公告)号：US20140117494A1

    公开(公告)日：2014-05-01

    申请号：US13661195

    申请日：2012-10-26

    Applicant: XILINX, INC.

    Inventor： Jing Jing ,  Shuxian Wu ,  Parag Upadhyaya

    IPC: H01L27/06

    CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit.

    Abstract translation: 在半导体集成电路内实现的电感器结构包括包括至少一个匝的导电材料的线圈和包围线圈的电流返回。 电流返回由半导体集成电路的多个互连的金属层形成。

    Capacitor structure in an integrated circuit
    6.
    发明授权
    Capacitor structure in an integrated circuit 有权
    集成电路中的电容结构

    公开(公告)号：US09524964B2

    公开(公告)日：2016-12-20

    申请号：US14460292

    申请日：2014-08-14

    Applicant: Xilinx, Inc.

    Inventor： Jing Jing ,  Shuxian Wu

    IPC: H01L21/02 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

    CPC classification number: H01L27/0805 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an example, a capacitor in an integrated circuit (IC), includes: a first finger capacitor formed in at least one layer of the IC having a first bus and a second bus; a second finger capacitor formed in the at least one layer of the IC having a first bus and a second bus, where a longitudinal edge of the second bus of the second finger capacitor is adjacent a longitudinal edge of the first bus of the first finger capacitor and separated by a dielectric gap; and a first metal segment formed on a first layer above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor.

    Abstract translation: 在一个示例中，集成电路（IC）中的电容器包括：形成在具有第一总线和第二总线的IC的至少一个层中的第一指状电容器; 形成在具有第一总线和第二总线的IC的至少一层中的第二手指电容器，其中第二指状电容器的第二总线的纵向边缘与第一指状电容器的第一总线的纵向边缘相邻 并由电介质间隙隔开; 以及形成在所述至少一层上方的第一层上的第一金属段，所述第一金属段电耦合到所述第一指状电容器的第一总线，并增加所述第一指状电容器的第一总线的宽度和高度。

    Substrate noise isolation structures for semiconductor devices
    9.
    发明授权
    Substrate noise isolation structures for semiconductor devices 有权

    公开(公告)号：US09923051B1

    公开(公告)日：2018-03-20

    申请号：US15272292

    申请日：2016-09-21

    Applicant: Xilinx, Inc.

    Inventor： Jing Jing ,  Shuxian Wu ,  Jane Sowards

    IPC: H01L29/06 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L29/78 ,  H01L21/761

    CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L21/823481

    Abstract: An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

    INTEGRATED CIRCUIT WITH SHIELDING STRUCTURES
    10.
    发明申请
    INTEGRATED CIRCUIT WITH SHIELDING STRUCTURES 审中-公开

    公开(公告)号：US20180076134A1

    公开(公告)日：2018-03-15

    申请号：US15267035

    申请日：2016-09-15

    Applicant: Xilinx, Inc.

    Inventor： Jing Jing ,  Shuxian Wu ,  Xin X. Wu ,  Parag Upadhyaya

    IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/64

    CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L23/645 ,  H01L28/10

    Abstract: A semiconductor device includes an interconnect structure disposed over a semiconductor substrate. The interconnect structure includes a first device disposed in a first portion of the interconnect structure. A first shielding plane including a first conductive material is disposed in a second portion of the interconnect structure over the first portion of the interconnect structure. A second device is disposed in a third portion of the interconnect structure over the second portion of the interconnect structure. An isolation wall including a second conductive material is disposed in the first, second, and third portions of the interconnect structure. The isolation wall is coupled to the first shielding plane, and surrounds the first device, the first shielding plane, and the second device.

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