公开(公告)号：US20240394453A1

公开(公告)日：2024-11-28

申请号：US18202465

申请日：2023-05-26

Applicant: Xilinx, Inc.

Inventor： Wuxi Li ,  Ismail Bustany ,  Yuji Kukimoto ,  Mehrdad Eslami Dehkordi

IPC: G06F30/392 ,  G06F30/31 ,  G06F30/3312

Abstract: A design tool calibrates current delays of timing arcs in a current placement of a circuit design by determining respective delta-delays of the timing arcs. The current placement is represented by timing nodes connected by the timing arcs in a graph. The calibrating is based on a first timer model indicating arrival times at the timing nodes based on timing propagation without accounting for timing exceptions, and a reference timer indicating slacks that account for timing exceptions at the timing nodes. The design tool updates the current delays of the timing arcs using the delta-delays and delays from the first timer model and updates the current placement based on the current delays. The updating of the current delays and updating of the current placement are repeated in response to failure to satisfy placement convergence criteria.