公开(公告)号：US20240394453A1

公开(公告)日：2024-11-28

申请号：US18202465

申请日：2023-05-26

Applicant: Xilinx, Inc.

Inventor： Wuxi Li ,  Ismail Bustany ,  Yuji Kukimoto ,  Mehrdad Eslami Dehkordi

IPC: G06F30/392 ,  G06F30/31 ,  G06F30/3312

Abstract: A design tool calibrates current delays of timing arcs in a current placement of a circuit design by determining respective delta-delays of the timing arcs. The current placement is represented by timing nodes connected by the timing arcs in a graph. The calibrating is based on a first timer model indicating arrival times at the timing nodes based on timing propagation without accounting for timing exceptions, and a reference timer indicating slacks that account for timing exceptions at the timing nodes. The design tool updates the current delays of the timing arcs using the delta-delays and delays from the first timer model and updates the current placement based on the current delays. The updating of the current delays and updating of the current placement are repeated in response to failure to satisfy placement convergence criteria.

公开(公告)号：US11645440B1

公开(公告)日：2023-05-09

申请号：US17062324

申请日：2020-10-02

Applicant: Xilinx, Inc.

Inventor： Ismail Bustany ,  Yifan Zhou

IPC: G06F30/3312 ,  G06F30/398 ,  G06N20/00 ,  G06N5/04 ,  G06F30/394 ,  G06F30/392 ,  G06F30/33 ,  G06F30/3315 ,  G06F111/06

CPC classification number: G06F30/3312 ,  G06F30/33 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06N5/04 ,  G06N20/00 ,  G06F30/3315 ,  G06F2111/06

Abstract: Training of a machine learning model used to infer estimated delays of circuit routes during placement and routing of a circuit design. Training can include selecting sample pairs of source pins and destination pins of an integrated circuit (IC) device, and determining respective delays of shortest paths that connect the source pins to the destination pins of the sample pairs based on a resistance-capacitance model of wires that form the shortest paths on the IC device. Respective sets of features are determined for the shortest paths, and the model is trained using the respective sets of features and the respective delays as labels. The machine learning model can be provided to an electronic design automation tool for estimating delays.