公开(公告)号：US20240394453A1

公开(公告)日：2024-11-28

申请号：US18202465

申请日：2023-05-26

Applicant: Xilinx, Inc.

Inventor： Wuxi Li ,  Ismail Bustany ,  Yuji Kukimoto ,  Mehrdad Eslami Dehkordi

IPC: G06F30/392 ,  G06F30/31 ,  G06F30/3312

Abstract: A design tool calibrates current delays of timing arcs in a current placement of a circuit design by determining respective delta-delays of the timing arcs. The current placement is represented by timing nodes connected by the timing arcs in a graph. The calibrating is based on a first timer model indicating arrival times at the timing nodes based on timing propagation without accounting for timing exceptions, and a reference timer indicating slacks that account for timing exceptions at the timing nodes. The design tool updates the current delays of the timing arcs using the delta-delays and delays from the first timer model and updates the current placement based on the current delays. The updating of the current delays and updating of the current placement are repeated in response to failure to satisfy placement convergence criteria.

公开(公告)号：US20240330558A1

公开(公告)日：2024-10-03

申请号：US18193197

申请日：2023-03-30

Applicant: Xilinx, Inc.

Inventor： Jichun Wang ,  Wuxi Li ,  Chun Zhang ,  Paul Kundarewich ,  John Blaine

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set. The circuit design is selectively modified by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set.

公开(公告)号：US20240265182A1

公开(公告)日：2024-08-08

申请号：US18105605

申请日：2023-02-03

Applicant: Xilinx, Inc.

Inventor： Wuxi Li ,  Mehrdad Eslami Dehkordi

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: Globally placing a circuit design includes adjusting indicated capacity levels for placement bins associated with a target integrated circuit, based on first levels of demand for resources by instances in the circuit design in regions of the target IC. Region constraints restrict placement of the instances in the regions, and the regions include two or more two or more overlapping regions. Tracked levels of demand for resources in the placement bins are adjusted, after adjusting the indicated capacity levels, based on the indicated capacity levels, a target utilization level of the resources in the placement bins, and a current placement. The current placement of the instances is updated based on a density gradient of an electrostatics-based model of the tracked levels of demand, and repeating adjusting the tracked levels of demand and updating the current placement are repeated in response to the density gradient failing to satisfy a threshold.

公开(公告)号：US10860765B1

公开(公告)日：2020-12-08

申请号：US16283552

申请日：2019-02-22

Applicant: Xilinx, Inc.

Inventor： Wuxi Li ,  Mehrdad Eslami Dehkordi ,  Xiaojian Yang

IPC: G06F17/50 ,  G06F30/34 ,  H03K19/17736 ,  G06F30/396

Abstract: Some examples described herein provide for clock tree generation for a programmable logic device, and more specifically, for clock tree generation in conjunction or simultaneous with placement of logic for a programmable logic device. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to: generate clock trees in conjunction with placing logic for an application to be implemented in a programmable logic region of a programmable logic device; generate data routes between the placed logic; and generate a physical implementation of the application based on the placed logic, the clock trees, and the data routes. The physical implementation is capable of being loaded on the programmable logic region of the programmable logic device.