Method and system for refreshing dynamic random access memory
    1.
    发明授权
    Method and system for refreshing dynamic random access memory 失效
    刷新动态随机存取存储器的方法和系统

    公开(公告)号:US08606991B2

    公开(公告)日:2013-12-10

    申请号:US12955112

    申请日:2010-11-29

    IPC分类号: G06F12/06

    CPC分类号: G11C11/406 G11C11/40618

    摘要: A method and system for refreshing DRAM having a plurality of banks, each of the banks including a plurality of rows includes dividing all banks in DRAM into a plurality of groups of banks, each of the groups having n banks, wherein n is an integer greater than or equal to 1. A threshold of available retention time for each group of banks is determined. Each row of banks in each group of banks is refreshed. Refreshing one row of a bank in one group of banks includes determining whether a refresh operation for the row of the bank conflicts with an access operation for the bank where the row of the bank is located. If there is a conflict, then it is determined whether to perform the refresh operation or the access operation for the current row of the bank. If it is determined to perform the access operation, the access operation is continued. If it is determined to perform the recess operation, the current row of the bank is refreshed. DRAM access performance is improved.

    摘要翻译: 一种用于刷新具有多个存储体的DRAM的方法和系统,每个存储体包括多行,包括将DRAM中的所有存储体划分成多个存储体组,每个组具有n个存储体,其中n是更大的整数 大于或等于1.确定每组银行可用保留时间的阈值。 每组银行中的每一行银行都被刷新。 刷新一组银行中的一行银行包括确定银行行的刷新操作是否与银行的行所在的银行的访问操作冲突。 如果存在冲突,则确定是否对银行的当前行执行刷新操作或访问操作。 如果确定执行访问操作,则继续访问操作。 如果确定执行凹槽操作,则刷新存储体的当前行。 DRAM访问性能得到提高。

    METHOD AND SYSTEM FOR REFRESHING DYNAMIC RANDOM ACCESS MEMORY
    2.
    发明申请
    METHOD AND SYSTEM FOR REFRESHING DYNAMIC RANDOM ACCESS MEMORY 失效
    用于刷新动态随机存取存储器的方法和系统

    公开(公告)号:US20110131371A1

    公开(公告)日:2011-06-02

    申请号:US12955112

    申请日:2010-11-29

    IPC分类号: G06F12/06

    CPC分类号: G11C11/406 G11C11/40618

    摘要: A method and system for refreshing DRAM having a plurality of banks, each of the banks including a plurality of rows includes dividing all banks in DRAM into a plurality of groups of banks, each of the groups having n banks, wherein n is an integer greater than or equal to 1. A threshold of available retention time for each group of banks is determined. Each row of banks in each group of banks is refreshed. Refreshing one row of a bank in one group of banks includes determining whether a refresh operation for the row of the bank conflicts with an access operation for the bank where the row of the bank is located. If there is a conflict, then it is determined whether to perform the refresh operation or the access operation for the current row of the bank. If it is determined to perform the access operation, the access operation is continued. If it is determined to perform the recess operation, the current row of the bank is refreshed. DRAM access performance is improved.

    摘要翻译: 一种用于刷新具有多个存储体的DRAM的方法和系统,每个存储体包括多行,包括将DRAM中的所有存储体划分成多个存储体组,每个组具有n个存储体,其中n是更大的整数 大于或等于1.确定每组银行可用保留时间的阈值。 每组银行中的每一行银行都被刷新。 刷新一组银行中的一行银行包括确定银行行的刷新操作是否与银行的行所在的银行的访问操作冲突。 如果存在冲突,则确定是否对银行的当前行执行刷新操作或访问操作。 如果确定执行访问操作,则继续访问操作。 如果确定执行凹槽操作,则刷新存储体的当前行。 DRAM访问性能得到提高。

    Segmented and overlapped skew tracking method for SERDES frame interface level 5
    3.
    发明授权
    Segmented and overlapped skew tracking method for SERDES frame interface level 5 失效
    SERDES帧接口级别5的分段和重叠偏斜跟踪方法

    公开(公告)号:US08340137B2

    公开(公告)日:2012-12-25

    申请号:US12775519

    申请日:2010-05-07

    IPC分类号: H04J3/06 H04L7/00 H04B17/00

    CPC分类号: H04B10/0795

    摘要: A method and device for performing skew detection on data transmitted over a data channel and a high speed optical communication interface including the device are disclosed, wherein data of a reference frame over a reference channel is composed sequentially of a reference data segment with a length of Umax over each of data channels to be subject to skew detection. The method includes: S1) performing the following on one frame of data transmitted over one data channel in a period of one frame: a) dividing the frame of data into a plurality of data blocks according to the maximum allowable skew detection range Rmax; b) dividing each of the data blocks into a plurality of segments each with the length of Umax; c) serially comparing each of the segments in the respective data blocks with the corresponding reference data segment, respectively, to derive skew detection results of all the segments in the respective data blocks; and d) for each of the data blocks, selecting the skew detection result of one of all the segments in the data block as a skew detection result of the data block; and S2) selecting a skew detection result with the maximum skew from among the skew detection results of all the data blocks as a skew detection result of the frame of data.

    摘要翻译: 公开了一种用于对通过数据信道发送的数据和包括该设备的高速光通信接口进行偏移检测的方法和装置,其中参考信道上的参考帧的数据由一个参考数据段的长度 每个数据通道上的Umax要经受歪斜检测。 该方法包括:S1)在一帧周期内通过一个数据信道发送的一帧数据执行以下操作:a)根据最大允许偏移检测范围Rmax将数据帧划分为多个数据块; b)将每个数据块划分成多个具有Umax长度的段; c)分别将各个数据块中的每个片段与相应的参考数据片段进行串行比较,以得到相应数据块中所有片段的偏移检测结果; 和d)对于每个数据块,选择数据块中所有段中的一个段的偏斜检测结果作为数据块的偏斜检测结果; 和S2)从所有数据块的倾斜检测结果中选择具有最大偏斜的偏斜检测结果作为数据帧的偏斜检测结果。

    Segmented and Overlapped skew tracking method for serdes frame interface Level 5
    4.
    发明申请
    Segmented and Overlapped skew tracking method for serdes frame interface Level 5 失效
    用于serdes帧接口的分段和重叠偏斜跟踪方法5级

    公开(公告)号:US20100306603A1

    公开(公告)日:2010-12-02

    申请号:US12775519

    申请日:2010-05-07

    IPC分类号: G06F11/07

    CPC分类号: H04B10/0795

    摘要: A method and device for performing skew detection on data transmitted over a data channel and a high speed optical communication interface including the device are disclosed, wherein data of a reference frame over a reference channel is composed sequentially of a reference data segment with a length of Umax over each of data channels to be subject to skew detection. The method includes: S1) performing the following on one frame of data transmitted over one data channel in a period of one frame: a) dividing the frame of data into a plurality of data blocks according to the maximum allowable skew detection range Rmax; b) dividing each of the data blocks into a plurality of segments each with the length of Umax; c) serially comparing each of the segments in the respective data blocks with the corresponding reference data segment, respectively, to derive skew detection results of all the segments in the respective data blocks; and d) for each of the data blocks, selecting the skew detection result of one of all the segments in the data block as a skew detection result of the data block; and S2) selecting a skew detection result with the maximum skew from among the skew detection results of all the data blocks as a skew detection result of the frame of data.

    摘要翻译: 公开了一种用于对通过数据信道发送的数据和包括该设备的高速光通信接口进行偏移检测的方法和装置,其中参考信道上的参考帧的数据由一个参考数据段的长度 每个数据通道上的Umax要经受歪斜检测。 该方法包括:S1)在一帧周期内通过一个数据信道发送的一帧数据执行以下操作:a)根据最大允许偏移检测范围Rmax将数据帧划分为多个数据块; b)将每个数据块划分成多个具有Umax长度的段; c)分别将各个数据块中的每个片段与相应的参考数据片段进行串行比较,以得到相应数据块中所有片段的偏移检测结果; 和d)对于每个数据块,选择数据块中所有段中的一个段的偏斜检测结果作为数据块的偏斜检测结果; 和S2)从所有数据块的倾斜检测结果中选择具有最大偏斜的偏斜检测结果作为数据帧的偏斜检测结果。

    Over-current detection circuit in a switch regulator

    公开(公告)号:US07145315B2

    公开(公告)日:2006-12-05

    申请号:US10966225

    申请日:2004-10-15

    申请人: Hong Wei Wang

    发明人: Hong Wei Wang

    IPC分类号: G05F1/40 H02H7/00 H02H7/10

    摘要: A switch regulator includes an inductor, a reference transistor, a first switching transistor, and a second switching transistor. The first switching transistor includes a gate electrode, a first main electrode (e.g., a source or a drain), and a second main electrode (e.g., a source or a drain). The first switching transistor is coupled in series with the inductor when it is turned on by a clock. The first main electrode (e.g., the source or the drain) of the switching transistor is connected to a ground or a fixed voltage power supply. A reference voltage may then be generated by flowing a current through the reference transistor. As such, the switch regulator contains an over-current detector that is flexible in size of current to be detected while consuming a relatively small amount of space and having substantially low cost on the overall efficiency of the switch regulator.