公开(公告)号：US20220102367A1

公开(公告)日：2022-03-31

申请号：US17101113

申请日：2020-11-23

申请人： YIELD MICROELECTRONICS CORP.

发明人： WEN-CHIEN HUANG ,  YU TING HUANG ,  CHI PEI WU

IPC分类号： H01L27/112

摘要： A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array.

公开(公告)号：US20230113604A1

公开(公告)日：2023-04-13

申请号：US17455546

申请日：2021-11-18

申请人： YIELD MICROELECTRONICS CORP.

发明人： YU TING HUANG ,  CHI PEI WU

IPC分类号： H01L27/112

摘要： A high writing rate antifuse array includes at least one sub-memory array including two antifuse memory cells arranged side by side between two neighboring bit lines. Each of two antifuse memory cells includes an antifuse transistor. The antifuse transistor has at least one sharp corner overlapping an antifuse gate above a first gate dielectric layer. Each of two antifuse memory cells includes a selection transistor. The second gate dielectric layers of two selection transistors are connected with each other. Thus, two antifuse memory cells are connected with the same select line and the same word line but are respectively connected with different bit lines. In the present invention, a common source contact is used, and two selection transistors share a channel, whereby to stabilize the source structure, increase the channel width of the selection transistors, and raise the writing rate without increase of overall area of the layout.

公开(公告)号：US20230230646A1

公开(公告)日：2023-07-20

申请号：US17698175

申请日：2022-03-18

申请人： YIELD MICROELECTRONICS CORP.

发明人： YU TING HUANG ,  CHI PEI WU

IPC分类号： G11C17/04 ,  H01L27/112 ,  H01L49/02 ,  G11C17/08

CPC分类号： G11C17/04 ,  H01L27/1122 ,  H01L28/40 ,  G11C17/08

摘要： A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

公开(公告)号：US20220181337A1

公开(公告)日：2022-06-09

申请号：US17248744

申请日：2021-02-05

申请人： YIELD MICROELECTRONICS CORP.

发明人： WEN-CHIEN HUANG ,  YU TING HUANG ,  CHI PEI WU

IPC分类号： H01L27/112

摘要： A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.

公开(公告)号：US20240260260A1

公开(公告)日：2024-08-01

申请号：US18186278

申请日：2023-03-20

申请人： YIELD MICROELECTRONICS CORP.

发明人： YU TING HUANG ,  CHI PEI WU

IPC分类号： H10B20/00 ,  G11C17/12

CPC分类号： H10B20/363 ,  G11C17/126

摘要： A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.