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    SMALL-AREA SIDE-CAPACITOR READ-ONLY MEMORY DEVICE, MEMORY ARRAY AND METHOD FOR OPERATING THE SAME
    1.
    发明公开
    SMALL-AREA SIDE-CAPACITOR READ-ONLY MEMORY DEVICE, MEMORY ARRAY AND METHOD FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20230230646A1

    公开(公告)日：2023-07-20

    申请号：US17698175

    申请日：2022-03-18

    申请人： YIELD MICROELECTRONICS CORP.

    发明人： YU TING HUANG ,  CHI PEI WU

    IPC分类号： G11C17/04 ,  H01L27/112 ,  H01L49/02 ,  G11C17/08

    CPC分类号： G11C17/04 ,  H01L27/1122 ,  H01L28/40 ,  G11C17/08

    摘要： A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

    FERROELECTRIC WRITE ONCE READ ONLY MEMORY FOR ARCHIVAL STORAGE
    3.
    发明申请
    FERROELECTRIC WRITE ONCE READ ONLY MEMORY FOR ARCHIVAL STORAGE 有权
    电磁写入只能存储存储存储

    公开(公告)号：US20030235066A1

    公开(公告)日：2003-12-25

    申请号：US10177082

    申请日：2002-06-21

    申请人： Micron Technology, Inc.

    发明人： Leonard Forbes

    IPC分类号： G11C011/22

    CPC分类号： G11C17/04 ,  G11C11/22

    摘要： Structures and methods for ferroelectric write once read only memory adapted to be programmed for long retention archival storage are provided. The write once read only memory cell includes a charge amplifier transistor. The transistor includes a source region, a drain region, and a channel region located between the source and the drain regions. A gate stack is located above the channel region. The gate stack includes; a gate oxide layer, a polysilicon interconnect on the gate oxide, a ferroelectric dielectric coupled to the polysilicon interconnect, and a control electrode coupled to the ferroelectric dielectric. A plug couples the source region to an array plate. A transmission line is coupled to the drain region.

    摘要翻译： 提供铁电写入的结构和方法一次只读存储器，适用于长时间保存归档存储器的编程。 一次写入只读存储单元包括一个电荷放大晶体管。 晶体管包括源极区，漏极区和位于源极和漏极区之间的沟道区。 栅极堆叠位于沟道区域上方。 门堆叠包括 栅极氧化物层，栅极氧化物上的多晶硅互连，耦合到多晶硅互连的铁电电介质，以及耦合到铁电电介质的控制电极。 插头将源区域耦合到阵列板。 传输线耦合到漏区。

    Differentially coupled memory arrays
    4.
    发明授权
    Differentially coupled memory arrays 失效
    不同的联接存储器阵列

    公开(公告)号：US3827032A

    公开(公告)日：1974-07-30

    申请号：US26400072

    申请日：1972-06-19

    申请人： INTEGRATED MEMORIES INC

    发明人： ABBOTT W ,  CHEN T

    IPC分类号： G11C17/04 ,  G11C11/24 ,  G11C17/00

    CPC分类号： G11C17/04

    摘要： A read-only memory plane has a plurality of storage elements arranged in a matrix of columns and rows. Drive means are associated with the columns of elements for energizing the elements and a plurality of sense lines are associated with the row of elements for determining the information content of the storage elements. A second matrix of storage elements is within the memory plane in tandem with the first matrix of elements. A second set of drive means and sense lines are provided for the read-out of the second array of storage elements. The information read-out is manifest in the presence or absence of signals induced in the sense lines when the storage elements are energized. Pairs of sense lines one in each pair from the first array and the other from the second array, are coupled to respective differential amplifiers for amplifying the induced signals and for rejecting any stray signals including background noise which would be common to the two arrays.

    摘要翻译： 只读存储器平面具有排列成列和行的矩阵的多个存储元件。 驱动装置与用于激励元件的元件列相关联，并且多个感测线与用于确定存储元件的信息内容的元件行相关联。 存储元件的第二矩阵在与存储器平面内的第一矩阵的元件之间。 第二组驱动装置和感测线被提供用于读出第二存储元件阵列。 当存储元件被通电时，在存在或不存在感测线中感应的信号的情况下，显示信息读出。 耦合到相应的差分放大器，用于放大感应信号和拒绝任何杂散信号，包括两个阵列共有的背景噪声。