公开(公告)号：US20120272201A1

公开(公告)日：2012-10-25

申请号：US13535242

申请日：2012-06-27

申请人： Ya-Chieh Lai ,  Frank Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

发明人： Ya-Chieh Lai ,  Frank Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

公开(公告)号：US08677301B2

公开(公告)日：2014-03-18

申请号：US13535225

申请日：2012-06-27

申请人： Ya-Chieh Lai ,  Frank Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

发明人： Ya-Chieh Lai ,  Frank Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

摘要翻译： 描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。 采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

公开(公告)号：US20090307642A1

公开(公告)日：2009-12-10

申请号：US12133563

申请日：2008-06-05

申请人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

发明人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

摘要翻译： 描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。 采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

公开(公告)号：US08381152B2

公开(公告)日：2013-02-19

申请号：US12133563

申请日：2008-06-05

申请人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

发明人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

摘要翻译： 描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。 采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

公开(公告)号：US08645887B2

公开(公告)日：2014-02-04

申请号：US13535242

申请日：2012-06-27

申请人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

发明人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

公开(公告)号：US20120272200A1

公开(公告)日：2012-10-25

申请号：US13535225

申请日：2012-06-27

申请人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

发明人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew Moskewicz ,  Srinivas Doddi ,  Junjiang Lei ,  Weiping Fang ,  Kuanghao Lay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

摘要翻译： 描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。 采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

公开(公告)号：US20100064269A1

公开(公告)日：2010-03-11

申请号：US12208167

申请日：2008-09-10

申请人： Ya-Chieh Lai ,  Matthew Moskewicz ,  Frank Gennari

发明人： Ya-Chieh Lai ,  Matthew Moskewicz ,  Frank Gennari

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing the original layout of an integrated circuit pattern. The pattern matcher processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet a design waiver. The pattern matcher generates a second layout pattern with the waived patterns marked. The design rule checker subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules.

摘要翻译： 根据本发明的各种实施例，提供了通过模式匹配增强的用于设计规则检查的系统和方法，其中设计规则检查器忽略在验证期间违反设计规则的布局的某些模式。 本发明的一个实施例包括接收包含集成电路图案的原始布局的第一布局图案。 模式匹配器处理布局模式并指定满足设计豁免的集成电路图案的某些模式。 模式匹配器生成第二个布局模式，并标记放弃的模式。 设计规则检查器随后处理标记的布局图案，并根据一组指定的设计规则验证除了第二布局图案的标记图案之外的所有图案。 设计规则检查器生成第三个布局模式，只有布局的未标记模式根据指定的设计规则进行验证。

公开(公告)号：US08086981B2

公开(公告)日：2011-12-27

申请号：US12208167

申请日：2008-09-10

申请人： Ya-Chieh Lai ,  Matthew Moskewicz ,  Frank Gennari

发明人： Ya-Chieh Lai ,  Matthew Moskewicz ,  Frank Gennari

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081

摘要： According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing the original layout of an integrated circuit pattern. The pattern matcher processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet a design waiver. The pattern matcher generates a second layout pattern with the waived patterns marked. The design rule checker subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules.

摘要翻译： 根据本发明的各种实施例，提供了通过模式匹配增强的用于设计规则检查的系统和方法，其中设计规则检查器忽略在验证期间违反设计规则的布局的某些模式。 本发明的一个实施例包括接收包含集成电路图案的原始布局的第一布局图案。 模式匹配器处理布局模式并指定满足设计豁免的集成电路图案的某些模式。 模式匹配器生成第二个布局模式，并标记放弃的模式。 设计规则检查器随后处理标记的布局图案，并根据一组指定的设计规则验证除了第二布局图案的标记图案之外的所有图案。 设计规则检查器生成第三个布局模式，只有布局的未标记模式根据指定的设计规则进行验证。

公开(公告)号：US20100083208A1

公开(公告)日：2010-04-01

申请号：US12241409

申请日：2008-09-30

申请人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew W. Moskewicz ,  Junjiang Lei ,  Weinong Lai

发明人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew W. Moskewicz ,  Junjiang Lei ,  Weinong Lai

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.

摘要翻译： 公开了一种用于执行电子设计的模式分类的方法。 这种方法的一个优点是它可以使用快速模式匹配技术来基于几何相似性对图案和标记进行分类。 以这种方式，通常在电子设计中识别的大量标记和热点可被归纳并压缩成更小的一组模式族。 这大大减少了必须单独分析的模式数量，大大减少了系统资源的数量和分析和验证电路设计所需的时间。

公开(公告)号：US08079005B2

公开(公告)日：2011-12-13

申请号：US12241409

申请日：2008-09-30

申请人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew W Moskewicz ,  Junjiang Lei ,  Weinong Lai

发明人： Ya-Chieh Lai ,  Frank E. Gennari ,  Matthew W Moskewicz ,  Junjiang Lei ,  Weinong Lai

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.

摘要翻译： 公开了一种用于执行电子设计的模式分类的方法。 这种方法的一个优点是它可以使用快速模式匹配技术来基于几何相似性对图案和标记进行分类。 以这种方式，通常在电子设计中识别的大量标记和热点可被归纳并压缩成更小的一组模式族。 这大大减少了必须单独分析的模式数量，大大减少了系统资源的数量和分析和验证电路设计所需的时间。