公开(公告)号：US07259634B2

公开(公告)日：2007-08-21

申请号：US10872066

申请日：2004-06-18

Applicant: Yair Rosenbaum ,  Shai Sade ,  Sergey Sofer ,  Emil Yehushua

Inventor： Yair Rosenbaum ,  Shai Sade ,  Sergey Sofer ,  Emil Yehushua

IPC: H03B27/00

CPC classification number: H03K5/133 ,  H03K2005/00156 ,  H03K2005/00247

Abstract: An arrangement (100) and method for a high precision and low distortion digital delay line with infinite delay. The digital delay line has an oscillating ring (110) with an odd number of inverting elements that triggers a counter (120). A comparator (130) compares the counter and the MSB of a given delay word. A line of inverters (150–159), double the odd number in the ring oscillator, is connected to a MUX (160) controlled by the LSB of the delay word.This provides the advantages of: high resolution due to use of a small, basic component, self-delay ring oscillator; small silicon area due to use of a special decoding scheme use the rings number to produce large delays; and easy implementation as a digital block in an integrated circuit using a standard cells library to build the ring and the decoder.

Abstract translation: 一种用于具有无限延迟的高精度和低失真数字延迟线的装置（100）和方法。 数字延迟线具有振荡环（110），其具有触发计数器（120）的奇数个反相元件。 比较器（130）比较给定延迟字的计数器和MSB。 在环形振荡器中奇数倍的一行反相器（150-159）连接到由延迟字的LSB控制的MUX（160）。 这提供了以下优点：由于使用小的基本部件，自延迟环形振荡器而产生高分辨率; 由于采用特殊的解码方案，小硅片面积使用戒指数量产生较大的延时; 并且在使用标准单元库构建环和解码器的集成电路中作为数字块轻松实现。

公开(公告)号：US07023195B2

公开(公告)日：2006-04-04

申请号：US10670683

申请日：2003-09-25

Applicant: Yair Rosenbaum ,  Sergey Sofer ,  Emil Yehushua

Inventor： Yair Rosenbaum ,  Sergey Sofer ,  Emil Yehushua

IPC: G01R23/12 ,  H03D3/24

CPC classification number: G01R29/26 ,  G01R25/00

Abstract: A digital test module (5) is provided for testing a phase locked loop circuit. The module (5) includes phase detection circuitry (10) for performing phase measurements of the phase locked loop circuit and analog test circuitry (20) for testing at least one analog element of the phase locked loop circuit. Frequency measurement circuitry (30) is provided for performing frequency measurements of the phase locked loop circuit, as is circuitry (40) for performing calibration and jitter measurements. In this way cycle-to-cycle and phase jitter measurements may be made. A calibration mechanism is provided allowing a process evaluation to be made and which allows the jitter data to be provided in a few seconds. The fully digital design facilitates easy manufacture and ready retargeting of the module to diverse applications and processes.

Abstract translation: 提供了用于测试锁相环电路的数字测试模块（5）。 模块（5）包括相位检测电路（10），用于执行锁相环电路和用于测试锁相环电路的至少一个模拟元件的模拟测试电路（20）的相位测量。 提供频率测量电路（30）用于执行锁相环电路的频率测量，电路（40）用于执行校准和抖动测量。 以这种方式，可以进行周期到周期和相位抖动测量。 提供了一种校准机制，允许进行过程评估，并且允许在几秒钟内提供抖动数据。 全数字化设计便于制造，并将模块准备好重新定位到各种应用和过程。